Misplaced Pages

This is a list of microprocessors designed by AMD containing a 3D integrated graphics processing unit (iGPU), including those under the AMD APU (Accelerated Processing Unit) product series.

Features overview

The following table shows features of AMD's processors with 3D graphics, including APUs.

• view
• talk
• edit

Platform			High, standard and low power														Low and ultra-low power
Codename	Server	Basic						Toronto
		Micro																Kyoto
	Desktop	Performance													Raphael	Phoenix
		Mainstream	Llano	Trinity	Richland	Kaveri	Kaveri Refresh (Godavari)	Carrizo	Bristol Ridge	Raven Ridge	Picasso	Renoir	Cezanne
		Entry
		Basic																Kabini				Dalí
	Mobile	Performance										Renoir	Cezanne	Rembrandt	Dragon Range
		Mainstream	Llano	Trinity	Richland	Kaveri		Carrizo	Bristol Ridge	Raven Ridge	Picasso	Renoir Lucienne	Cezanne Barceló			Phoenix
		Entry																				Dalí			Mendocino
		Basic															Desna, Ontario, Zacate	Kabini, Temash	Beema, Mullins	Carrizo-L	Stoney Ridge		Pollock
	Embedded			Trinity		Bald Eagle		Merlin Falcon, Brown Falcon		Great Horned Owl		Grey Hawk					Ontario, Zacate	Kabini	Steppe Eagle, Crowned Eagle, LX-Family		Prairie Falcon	Banded Kestrel		River Hawk
Released			Aug 2011	Oct 2012	Jun 2013	Jan 2014	2015	Jun 2015	Jun 2016	Oct 2017	Jan 2019	Mar 2020	Jan 2021	Jan 2022	Sep 2022	Jan 2023	Jan 2011	May 2013	Apr 2014	May 2015	Feb 2016	Apr 2019	Jul 2020	Jun 2022	Nov 2022
CPU microarchitecture			K10	Piledriver		Steamroller		Excavator	"Excavator+"	Zen	Zen+	Zen 2	Zen 3	Zen 3+	Zen 4		Bobcat	Jaguar	Puma	Puma+	"Excavator+"	Zen		Zen+	"Zen 2+"
ISA			x86-64 v1	x86-64 v2				x86-64 v3							x86-64 v4		x86-64 v1	x86-64 v2			x86-64 v3
Socket	Desktop	Performance	—												AM5	—	—
		Mainstream	—					AM4						—		—
		Entry	FM1	FM2		FM2+		FM2+, AM4	AM4					—
		Basic	—														—	AM1	—			FP5	—
	Other		FS1	FS1+, FP2		FP3		FP4		FP5		FP6		FP7	FL1	FP7 FP7r2 FP8	?	FT1	FT3	FT3b		FP4	FP5	FT5	FP5	FT6
PCI Express version			2.0			3.0								4.0	5.0	4.0	2.0				3.0
CXL			—														—
Fab. (nm)			GF 32SHP (HKMG SOI)			GF 28SHP (HKMG bulk)				GF 14LPP (FinFET bulk)	GF 12LP (FinFET bulk)	TSMC N7 (FinFET bulk)		TSMC N6 (FinFET bulk)	CCD: TSMC N5 (FinFET bulk) cIOD: TSMC N6 (FinFET bulk)	TSMC 4nm (FinFET bulk)	TSMC N40 (bulk)	TSMC N28 (HKMG bulk)	GF 28SHP (HKMG bulk)			GF 14LPP (FinFET bulk)		GF 12LP (FinFET bulk)	TSMC N6 (FinFET bulk)
Die area (mm)			228	246		245		245	250	210		156	180	210	CCD: (2x) 70 cIOD: 122	178	75 (+ 28 FCH)	107		?	125	149			~100
Min TDP (W)			35	17				12				10		15	65	35	4.5	4	3.95	10	6			12	8
Max APU TDP (W)			100			95		65						45	170	54	18	25					6	54	15
Max stock APU base clock (GHz)			3	3.8	4.1	4.1		3.7	3.8	3.6	3.7	3.8	4.0	3.3	4.7	4.3	1.75	2.2	2	2.2	3.2	2.6	1.2	3.35	2.8
Max APUs per node			1														1
Max core dies per CPU			1												2	1	1
Max CCX per core die			1									2	1				1
Max cores per CCX			4										8				2	4			2			4
Max CPU cores per APU			4									8			16	8	2	4			2			4
Max threads per CPU core			1							2							1					2
Integer pipeline structure			3+3	2+2						4+2		4+2+1	1+3+3+1+2				1+1+1+1				2+2	4+2			4+2+1
i386, i486, i586, CMOV, NOPL, i686, PAE, NX bit, CMPXCHG16B, AMD-V, RVI, ABM, and 64-bit LAHF/SAHF
IOMMU			—	v2													v1		v2
BMI1, AES-NI, CLMUL, and F16C																	—
MOVBE			—
AVIC, BMI2, RDRAND, and MWAITX/MONITORX																	—
SME, TSME, ADX, SHA, RDSEED, SMAP, SMEP, XSAVEC, XSAVES, XRSTORS, CLFLUSHOPT, CLZERO, and PTE Coalescing			—														—
GMET, WBNOINVD, CLWB, QOS, PQE-BW, RDPID, RDPRU, and MCOMMIT			—														—
MPK, VAES			—														—
SGX			—														—
FPUs per core			1	0.5						1							1				0.5	1
Pipes per FPU			2														2
FPU pipe width			128-bit									256-bit					80-bit	128-bit							256-bit
CPU instruction set SIMD level			SSE4a	AVX				AVX2							AVX-512		SSSE3	AVX			AVX2
3DNow!			3DNow!+	—													—
PREFETCH/PREFETCHW
GFNI			—														—
AMX			—
FMA4, LWP, TBM, and XOP			—							—							—					—
FMA3
AMD XDNA			—														—
L1 data cache per core (KiB)			64	16				32									32
L1 data cache associativity (ways)			2	4				8									8
L1 instruction caches per core			1	0.5						1							1				0.5	1
Max APU total L1 instruction cache (KiB)			256	128		192				256					512	256	64		128		96	128
L1 instruction cache associativity (ways)			2			3				4		8					2				3	4			8
L2 caches per core			1	0.5						1							1				0.5	1
Max APU total L2 cache (MiB)			4					2				4			16		1	2			1			2
L2 cache associativity (ways)			16							8							16					8
Max on--die L3 cache per CCX (MiB)			—							4			16		32		—						4
Max 3D V-Cache per CCD (MiB)										—					64	—							—
Max total in-CCD L3 cache per APU (MiB)										4		8	16		64								4
Max. total 3D V-Cache per APU (MiB)										—					64	—							—
Max. board L3 cache per APU (MiB)										—													—
Max total L3 cache per APU (MiB)										4		8	16		128								4
APU L3 cache associativity (ways)										16													16
L3 cache scheme										Victim													Victim
Max. L4 cache			—														—
Max stock DRAM support			DDR3-1866		DDR3-2133			DDR3-2133, DDR4-2400	DDR4-2400	DDR4-2933		DDR4-3200, LPDDR4-4266		DDR5-4800, LPDDR5-6400	DDR5-5200	DDR5-5600, LPDDR5x-7500	DDR3L-1333	DDR3L-1600	DDR3L-1866		DDR3-1866, DDR4-2400	DDR4-2400	DDR4-1600	DDR4-3200	LPDDR5-5500
Max DRAM channels per APU			2														1					2	1	2
Max stock DRAM bandwidth (GB/s) per APU			29.866		34.132			38.400		46.932		68.256		102.400	83.200	120.000	10.666	12.800	14.933		19.200	38.400	12.800	51.200	88.000
GPU microarchitecture			TeraScale 2 (VLIW5)	TeraScale 3 (VLIW4)		GCN 2nd gen		GCN 3rd gen		GCN 5th gen				RDNA 2		RDNA 3	TeraScale 2 (VLIW5)	GCN 2nd gen			GCN 3rd gen	GCN 5th gen			RDNA 2
GPU instruction set			TeraScale instruction set			GCN instruction set								RDNA instruction set			TeraScale instruction set	GCN instruction set							RDNA instruction set
Max stock GPU base clock (MHz)			600	800	844	866		1108		1250	1400	2100		2400	400		538	600	?	847	900	1200	600	1300	1900
Max stock GPU base GFLOPS			480	614.4	648.1	886.7		1134.5		1760	1971.2	2150.4		3686.4	102.4		86	?	?	?	345.6	460.8	230.4	1331.2	486.4
3D engine			Up to 400:20:8	Up to 384:24:6		Up to 512:32:8				Up to 704:44:16		Up to 512:32:8		768:48:8	128:8:4		80:8:4	128:8:4			Up to 192:12:8	Up to 192:12:4	192:12:4	Up to 512:?:?	128:?:?
			IOMMUv1			IOMMUv2											IOMMUv1		?		IOMMUv2
Video decoder			UVD 3.0			UVD 4.2		UVD 6.0		VCN 1.0		VCN 2.1	VCN 2.2	VCN 3.1		?	UVD 3.0	UVD 4.0	UVD 4.2		UVD 6.2	VCN 1.0			VCN 3.1
Video encoder			—	VCE 1.0		VCE 2.0		VCE 3.1									—	VCE 2.0			VCE 3.4
AMD Fluid Motion
GPU power saving			PowerPlay	PowerTune													PowerPlay	PowerTune
TrueAudio			—										?				—
FreeSync						1 2												1 2
HDCP			?			1.4				2.2				2.3			?	1.4				2.2			2.3
PlayReady			—							3.0 not yet							—					3.0 not yet
Supported displays			2–3	2–4				3		3 (desktop) 4 (mobile, embedded)		4					2				3	4		4
/drm/radeon									—												—
/drm/amdgpu			—														—

1. For FM2+ Excavator models: A8-7680, A6-7480 & Athlon X4 845.
2. A PC would be one node.
3. An APU combines a CPU and a GPU. Both have cores.
4. Requires firmware support.
5. ^ Requires firmware support.
6. No SSE4. No SSSE3.
7. Single-precision performance is calculated from the base (or boost) core clock speed based on a FMA operation.
8. Unified shaders : texture mapping units : render output units
9. ^ To play protected video content, it also requires card, operating system, driver, and application support. A compatible HDCP display is also needed for this. HDCP is mandatory for the output of certain audio formats, placing additional constraints on the multimedia setup.
10. To feed more than two displays, the additional panels must have native DisplayPort support. Alternatively active DisplayPort-to-DVI/HDMI/VGA adapters can be employed.
11. ^ DRM (Direct Rendering Manager) is a component of the Linux kernel. Support in this table refers to the most current version.

Graphics API overview

The following table shows the graphics and compute APIs support across ATI/AMD GPU microarchitectures. Note that a branding series might include older generation chips.

• view
• talk
• edit

Chip series	Micro­architecture	Fab	Supported APIs					AMD support	Year introduced	Introduced with
			Rendering			Computing / ROCm
			Vulkan	OpenGL	Direct3D	HSA	OpenCL
Wonder	Fixed-pipeline	1000 nm 800 nm	—	—	—	—	—	Ended	1986	Graphics Solutions
Mach		800 nm 600 nm							1991	Mach8
3D Rage		500 nm			5.0				1996	3D Rage
Rage Pro		350 nm		1.1	6.0				1997	Rage Pro
Rage 128		250 nm		1.2					1998	Rage 128 GL/VR
R100		180 nm 150 nm		1.3	7.0				2000	Radeon
R200	Programmable pixel & vertex pipelines	150 nm			8.1				2001	Radeon 8500
R300		150 nm 130 nm 110 nm		2.0	9.0 11 (FL 9_2)				2002	Radeon 9700
R420		130 nm 110 nm			9.0b 11 (FL 9_2)				2004	Radeon X800
R520		90 nm 80 nm			9.0c 11 (FL 9_3)				2005	Radeon X1800
R600	TeraScale 1	80 nm 65 nm		3.3	10.0 11 (FL 10_0)		ATI Stream		2007	Radeon HD 2900 XT
RV670		55 nm			10.1 11 (FL 10_1)		ATI Stream APP			Radeon HD 3850/3870
RV770		55 nm 40 nm					1.0		2008	Radeon HD 4850/4870
Evergreen	TeraScale 2	40 nm		4.5 (Linux 4.2)	11 (FL 11_0)		1.2		2009	Radeon HD 5850/5870
Northern Islands	TeraScale 2 TeraScale 3								2010	Radeon HD 6850/6870 Radeon HD 6950/6970
Southern Islands	GCN 1 gen	28 nm	1.0	4.6	11 (FL 11_1) 12 (FL11_1)		1.2 2.0 possible		2012	Radeon HD 7950/7970
Sea Islands	GCN 2 gen		1.2		11 (FL 12_0) 12 (FL 12_0)		2.0 (1.2 in MacOS, Linux) 2.1 Beta in Linux ROCm 2.2 possible		2013	Radeon HD 7790
Volcanic Islands	GCN 3 gen								2014	Radeon R9 285
Arctic Islands	GCN 4 gen	28 nm 14 nm	1.2 1.3 (GCN 4)					Supported	2016	Radeon RX 480
Polaris									2017	Radeon 520/530 Radeon RX 530/550/570/580
Vega	GCN 5 gen	14 nm 7 nm	1.3		11 (FL 12_1) 12 (FL 12_1)				2017	Radeon Vega Frontier Edition
Navi	RDNA	7 nm							2019	Radeon RX 5700 (XT)
Navi 2X	RDNA 2	7 nm 6 nm			11 (FL 12_1) 12 (FL 12_2)				2020	Radeon RX 6800 (XT)
Navi 3X	RDNA 3	6 nm 5 nm							2022	Radeon RX 7900 XT(X)

1. Radeon 7000 Series has programmable pixel shaders, but do not fully comply with DirectX 8 or Pixel Shader 1.0. See article on R100's pixel shaders.
2. These series do not fully comply with OpenGL 2+ as the hardware does not support all types of non-power-of-two (NPOT) textures.
3. OpenGL 4+ compliance requires supporting FP64 shaders and these are emulated on some TeraScale chips using 32-bit hardware.

Desktop processors with 3D graphics

APU or Radeon Graphics branded

Lynx: "Llano" (2011)

• Socket FM1
• CPU: K10 (also Husky or K10.5) cores with an upgraded Stars architecture, no L3 cache
  • L1 cache: 64 KB Data per core and 64 KB Instruction cache per core
  • L2 cache: 512 KB on dual-core, 1 MB on tri- and quad-core models
  • MMX, Enhanced 3DNow!, SSE, SSE2, SSE3, SSE4a, ABM, NX bit, AMD64, Cool'n'Quiet, AMD-V
• GPU: TeraScale 2 (Evergreen); all A and E series models feature Redwood-class integrated graphics on die (BeaverCreek for the dual-core variants and WinterPark for the quad-core variants). Sempron and Athlon models exclude integrated graphics.
• List of embedded GPU's
• Support for up to four DIMMs of up to DDR3-1866 memory
• Fabrication 32 nm on GlobalFoundries SOI process; Die size: 228 mm, with 1.178 billion transistors
• 5 GT/s UMI
• Integrated PCIe 2.0 controller
• Select models support Turbo Core technology for faster CPU operation when the thermal specification permits
• Select models support Hybrid Graphics technology to assist a discrete Radeon HD 6450, 6570, or 6670 discrete graphics card. This is similar to the Hybrid CrossFireX technology available in the AMD 700 and 800 chipset series

1. AMD in its technical documentation uses KB, which it defines as Kilobyte and as equal to 1024 bytes, and MB, which it defines as Megabyte and as equal to 1024 KB.
2. Single-precision performance is calculated from the base (or boost) core clock speed based on a FMA operation.

1. Models with "K" suffixes feature an unlocked multiplier and overclockable GPU.

Virgo: "Trinity" (2012)

• Fabrication 32 nm on GlobalFoundries SOI process
• Socket FM2
• CPU: Piledriver
  • L1 Cache: 16 KB Data per core and 64 KB Instructions per module
• GPU TeraScale 3 (VLIW4)
• Die Size: 246 mm, 1.303 Billion transistors
• Support for up to four DIMMs of up to DDR3-1866 memory
• 5 GT/s UMI
• GPU (based on VLIW4 architecture) instruction support: DirectX 11, Opengl 4.2, DirectCompute, Pixel Shader 5.0, Blu-ray 3D, OpenCL 1.2, AMD Stream, UVD3
• Integrated PCIe 2.0 controller, and Turbo Core technology for faster CPU/GPU operation when the thermal specification permits
• MMX, SSE, SSE2, SSE3, SSSE3, SSE4a, SSE4.1, SSE4.2, AMD64, AMD-V, AES, CLMUL, AVX, XOP, FMA3, FMA4, F16C, ABM, BMI1, TBM
• Sempron and Athlon models exclude integrated graphics
• Select models support Hybrid Graphics technology to assist a Radeon HD 7350, 7450, 7470, 7550, 7570, 7670 discrete graphics card. However, it has been found that this does not always improve 3D accelerated graphics performance.

1. AMD in its technical documentation uses KB, which it defines as Kilobyte and as equal to 1024 bytes, and MB, which it defines as Megabyte and as equal to 1024 KB.
2. Single-precision performance is calculated from the base (or boost) core clock speed based on a FMA operation.

"Richland" (2013)

• Fabrication 32 nm on GlobalFoundries SOI process
• Socket FM2
• Two or four CPU cores based on the Piledriver microarchitecture
  • Die Size: 246 mm, 1.303 Billion transistors
  • L1 Cache: 16 KB Data per core and 64 KB Instructions per module
  • MMX, SSE, SSE2, SSE3, SSSE3, SSE4a, SSE4.1, SSE4.2, AMD64, AMD-V, AES, AVX, AVX1.1, XOP, FMA3, FMA4, F16C, ABM, BMI1, TBM, Turbo Core 3.0, NX bit, PowerNow!
• GPU
  • TeraScale 3 architecture
  • HD Media Accelerator, AMD Hybrid Graphics

1. AMD in its technical documentation uses KB, which it defines as Kilobyte and as equal to 1024 bytes, and MB, which it defines as Megabyte and as equal to 1024 KB.
2. Single-precision performance is calculated from the base (or boost) core clock speed based on a FMA operation.

"Kabini" (2013, SoC)

• Fabrication 28 nm by GlobalFoundries
• Socket AM1, aka Socket FS1b (AM1 platform)
• 2 to 4 CPU Cores (Jaguar (microarchitecture))
• L1 Cache: 32 KB Data per core and 32 KB Instructions per core
• MMX, SSE, SSE2, SSE3, SSSE3, SSE4a, SSE4.1, SSE4.2, AMD64, AVX, F16C, CLMUL, AES, MOVBE (Move Big-Endian instruction), XSAVE/XSAVEOPT, ABM, BMI1, AMD-V support
• SoC with integrated memory, PCIe, 2× USB 3.0, 6× USB 2.0, Gigabit Ethernet, and 2× SATA III (6 Gb/s) controllers
• GPU based on Graphics Core Next (GCN)

1. AMD in its technical documentation uses KB, which it defines as Kilobyte and as equal to 1024 bytes, and MB, which it defines as Megabyte and as equal to 1024 KB.
2. Single-precision performance is calculated from the base (or boost) core clock speed based on a FMA operation.

"Kaveri" (2014) & "Godavari" (2015)

• Fabrication 28 nm by GlobalFoundries.
• Socket FM2+, support for PCIe 3.0.
• Two or four CPU cores based on the Steamroller microarchitecture.
  • Kaveri refresh models have codename Godavari.
• Die Size: 245 mm, 2.41 Billion transistors.
• L1 Cache: 16 KB Data per core and 96 KB Instructions per module.
• MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, SSE4a, AMD64, AMD-V, AES, CLMUL, AVX, AVX 1.1, XOP, FMA3, FMA4, F16C, ABM, BMI1, TBM, Turbo Core
• Three to eight Compute Units (CUs) based on GCN 2nd gen microarchitecture; 1 Compute Unit (CU) consists of 64 Unified Shader Processors : 4 Texture Mapping Units (TMUs) : 1 Render Output Unit (ROPs).
• Heterogeneous System Architecture-enabled zero-copy through pointer passing.
• SIP blocks: Unified Video Decoder, Video Coding Engine, TrueAudio.
• Dual-channel (2× 64 Bit) DDR3 memory controller.
• Integrated custom ARM Cortex-A5 co-processor with TrustZone Security Extensions in select APU models, except the Performance APU models.
• Select models support Hybrid Graphics technology by using a Radeon R7 240 or R7 250 discrete graphics card.
• Display controller: AMD Eyefinity 2, 4K Ultra HD support, DisplayPort 1.2 Support.

1. ^ AMD in its technical documentation uses KB, which it defines as Kilobyte and as equal to 1024 bytes, and MB, which it defines as Megabyte and as equal to 1024 KB.
2. ^ Single-precision performance is calculated from the base (or boost) core clock speed based on a FMA operation.

"Carrizo" (2016)

• Fabrication: 28 nm by GlobalFoundries
• Socket FM2+ or AM4, support for PCIe 3.0
• Two or four CPU cores based on the Excavator microarchitecture
• Die size: 250.04 mm, 3.1 billion transistors
• L1 cache: 32 KB data per core and 96 KB instructions per module
• MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, SSE4a, AMD64, AMD-V, AES, CLMUL, AVX, AVX 1.1, AVX2, XOP, FMA3, FMA4, F16C, ABM, BMI1, BMI2, TBM, RDRAND, Turbo Core
• Single- or dual-channel DDR3 or DDR4 memory controller
• Third generation GCN-based GPU (Radeon M300)
• Integrated custom ARM Cortex-A5 coprocessor with TrustZone security extensions

1. With cooler if available.
2. AMD in its technical documentation uses KB, which it defines as Kilobyte and as equal to 1024 bytes, and MB, which it defines as Megabyte and as equal to 1024 KB.
3. Single-precision performance is calculated from the base (or boost) core clock speed based on a FMA operation.

"Bristol Ridge" (2016)

• Fabrication 28 nm by GlobalFoundries
• Socket AM4, support for PCIe 3.0
• Two or four "Excavator+" CPU cores
• L1 Cache: 32 KB Data per core and 96 KB Instructions per module
• MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, SSE4a, AMD64, AMD-V, AES, CLMUL, AVX, AVX 1.1, AVX2, XOP, FMA3, FMA4, F16C, ABM, BMI1, BMI2, TBM, RDRAND, Turbo Core
• Dual-channel DDR4 memory controller
• PCI Express 3.0 x8 (No Bifurcation support, requires a PCI-e switch for any configuration other than x8)
• PCI Express 3.0 x4 as link to optional external chipset
• 4x USB 3.1 Gen 1
• Storage: 2x SATA and 2x NVMe or 2x PCI Express
• Third Generation GCN based GPU with hybrid VP9 decoding

1. With cooler if available.
2. AMD in its technical documentation uses KB, which it defines as Kilobyte and as equal to 1024 bytes, and MB, which it defines as Megabyte and as equal to 1024 KB.
3. Single-precision performance is calculated from the base (or boost) core clock speed based on a FMA operation.

"Raven Ridge" (2018)

• Fabrication 14 nm by GlobalFoundries
• Transistors: 4.94 billion
• Die size: 210 mm²
• Socket AM4
• Zen CPU cores
• MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, SSE4a, AMD64, AMD-V, AES, CLMUL, AVX, AVX 1.1, AVX2, FMA3, F16C, ABM, BMI1, BMI2, RDRAND, Turbo Core
• Dual-channel DDR4 memory controller
• Fifth generation GCN based GPU
• Video Core Next (VCN) 1.0

Common features of Zen based Raven Ridge desktop APUs:

• Socket: AM4.
• All the CPUs support DDR4-2666 (DDR4-2933 Ryzen) in dual-channel mode.
• L1 cache: 96 KB (32 KB data + 64 KB instruction) per core.
• L2 cache: 512 KB per core.
• All the CPUs support 16 PCIe 3.0 lanes.
• Includes integrated GCN 5th generation GPU.
• Fabrication process: GlobalFoundries 14LP.

• v
• t
• e

1. Unified shaders : Texture mapping units : Render output units and Compute units (CU)
2. Single-precision performance is calculated from the base (or boost) core clock speed based on a FMA operation.

"Picasso" (2019)

• Fabrication 12 nm by GlobalFoundries
• Transistors: 4.94 billion
• Die size: 210 mm²
• Socket AM4
• Zen+ CPU cores
• MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, SSE4a, AMD64, AMD-V, AES, CLMUL, AVX, AVX 1.1, AVX2, FMA3, F16C, ABM, BMI1, BMI2, RDRAND, Turbo Core
• Dual-channel DDR4 memory controller
• Fifth generation GCN based GPU
• Video Core Next (VCN) 1.0

Common features of Zen+ based desktop APUs:

• Socket: AM4.
• All the CPUs support DDR4-2933 in dual-channel mode, while Athlon Pro 300GE and Athlon Silver Pro 3125GE support only DDR4-2666.
• L1 cache: 96 KB (32 KB data + 64 KB instruction) per core.
• L2 cache: 512 KB per core.
• All the CPUs support 16 PCIe 3.0 lanes.
• Includes integrated GCN 5th generation GPU.
• Fabrication process: GlobalFoundries 12LP.

• v
• t
• e

1. Starting with 2020 releases, AMD stopped referring to integrated graphics as "Vega", therefore all Vega based iGPUs are branded as AMD Radeon Graphics (instead Radeon Vega 3 or Radeon Vega 10).
2. Unified shaders : Texture mapping units : Render output units and Compute units (CU)
3. Single-precision performance is calculated from the base (or boost) core clock speed based on a FMA operation.

"Renoir" (2020)

• Fabrication 7 nm by TSMC
• Socket AM4
• Up to eight Zen 2 CPU cores
• Dual-channel DDR4 memory controller

Common features of Ryzen 4000 desktop APUs:

• Socket: AM4.
• All the CPUs support DDR4-3200 in dual-channel mode.
• L1 cache: 64 KB (32 KB data + 32 KB instruction) per core.
• L2 cache: 512 KB per core.
• All the CPUs support 24 PCIe 3.0 lanes. 4 of the lanes are reserved as link to the chipset.
• Includes integrated GCN 5th generation GPU.
• Fabrication process: TSMC 7FF.

• v
• t
• e

1. Core complexes (CCXs) × cores per CCX
2. Unified shaders : Texture mapping units : Render output units and Compute units (CU)
3. Single-precision performance is calculated from the base (or boost) core clock speed based on a FMA operation.

1. ^ Model also available as PRO version as 4350GE, 4350G, 4650GE, 4650G, 4750GE, 4750G, released on July 21, 2020 for OEM only.
2. All of the iGPUs are branded as AMD Radeon Graphics.

"Cezanne" (2021)

• Fabrication 7 nm by TSMC
• Socket AM4
• Up to eight Zen 3 CPU cores
• Dual-channel DDR4 memory controller

Common features of Ryzen 5000 desktop APUs:

• Socket: AM4.
• All the CPUs support DDR4-3200 in dual-channel mode.
• L1 cache: 64 KB (32 KB data + 32 KB instruction) per core.
• L2 cache: 512 KB per core.
• All the CPUs support 24 PCIe 3.0 lanes. 4 of the lanes are reserved as link to the chipset.
• Includes integrated GCN 5th generation GPU.
• Fabrication process: TSMC 7FF.

• v
• t
• e

1. Core Complexes (CCX) × cores per CCX
2. Unified shaders : texture mapping units : render output units and compute units (CU)
3. Single precision performance is calculated from the base (or boost) core clock speed based on a FMA operation.

1. All of the iGPUs are branded as AMD Radeon Graphics.
2. ^ Model also available as PRO version as 5350GE, 5350G, 5650GE, 5650G, 5750GE, 5750G, released June 1, 2021.

Non APU or Radeon Graphics branded

"Raphael" (2022)

• Fabrication 5 nm (CCD) and 6 nm (cIOD) by TSMC
• Socket AM5
• Up to sixteen Zen 4 CPU cores
• Dual-channel DDR5 memory controller

• Basic iGPU

Common features of Ryzen 7000 desktop CPUs:

• Socket: AM5.
• All the CPUs support DDR5-5200 in dual-channel mode.
• L1 cache: 64 KB (32 KB data + 32 KB instruction) per core.
• L2 cache: 1 MB per core.
• All the CPUs support 28 PCIe 5.0 lanes. 4 of the lanes are reserved as link to the chipset.
• Includes integrated RDNA 2 GPU on the I/O die with 2 CUs and clock speeds of 400 MHz (base), 2.2 GHz (boost). Models with "F" suffixes are without iGPUs.
• Fabrication process: TSMC N5 FinFET (N6 FinFET for the I/O die).

• v
• t
• e

1. Self identifies as "AMD Radeon Graphics". See RDNA 2 § Integrated graphics processors (iGPs).
2. Core Complexes (CCX) × cores per CCX
3. ^ Only one of the two CCXes has additional 64 MB 3D V-Cache. Only the CCX without 3D V-Cache will be able to reach the maximum boost clocks. The CCX with 3D V-Cache will clock lower.
4. Release date for US, where it is only sold though MicroCenter. In Europe it is only available in Germany, and only through MindFactory, which released it on September 5, 2024.

"Phoenix" (2024)

Common features of Ryzen 8000G desktop APUs:

• Socket: AM5.
• All the CPUs support DDR5-5200 RAM in dual-channel mode in 2x1R and 2x2R configuration, but only DDR5-3600 for 4x1R and 4x2R.
• L1 cache: 64 KB (32 KB data + 32 KB instruction) per core.
• L2 cache: 1 MB per core.
• Models with Zen 4c cores (codenamed Phoenix 2) support 14 PCIe 4.0 lanes, while models without them support 20 lanes. 4 of the lanes are reserved as link to the chipset.
• Includes integrated RDNA 3 GPU.
• Includes XDNA AI Engine (Ryzen AI) on models without Zen 4c cores.
• Fabrication process: TSMC 4 nm FinFET.

• v
• t
• e

1. Core Complexes (CCX) × cores per CCX, or Zen 4 + Zen 4c cores
2. Unified shaders : Texture mapping units : Render output units : Ray accelerators : AI accelerators and Compute units (CU)
3. GPUs based on RDNA 3 have dual-issue stream processors so that up to two shader instructions can be executed per clock cycle under certain parallelism conditions.
4. ^ Model also available as PRO version as 8300G,, 8500G,, 8600G,, 8700G,
5. ^ Zen 4 cores' base frequency / Zen 4c cores' base frequency
6. ^ Zen 4 cores' boost frequency / Zen 4c cores' boost frequency

Server APUs

Opteron X2100-series "Kyoto" (2013) & "Steppe Eagle" (2016)

• Fabrication 28 nm
• Socket FT3 (BGA)
• 4 CPU Cores (Jaguar & Puma microarchitecture)
• L1 Cache: 32 KB Data per core and 32 KB Instructions per core
• MMX, SSE, SSE2, SSE3, SSSE3, SSE4a, SSE4.1, SSE4.2, AVX, F16C, CLMUL, AES, MOVBE (Move Big-Endian instruction), XSAVE/XSAVEOPT, ABM, BMI1, AMD-V support
• Single-channel DDR3 memory controller
• Turbo Dock Technology, C6 and CC6 low power states
• GPU based on 2nd generation Graphics Core Next (GCN) architecture

1. AMD in its technical documentation uses KB, which it defines as Kilobyte and as equal to 1024 bytes, and MB, which it defines as Megabyte and as equal to 1024 KB.
2. Single-precision performance is calculated from the base (or boost) core clock speed based on a FMA operation.

Opteron X3000-series "Toronto" (2017)

• Fabrication 28 nm
• Socket FP4 (BGA)
• Two or Four CPU cores based on the Excavator microarchitecture
• L1 Cache: 32 KB Data per core and 96 KB Instructions per module
• MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, SSE4a, AMD64, AMD-V, AES, CLMUL, AVX, AVX 1.1, AVX2, XOP, FMA3, FMA4, F16C, ABM, BMI1, BMI2, TBM, RDRAND
• Dual-channel DDR4 memory controller
• GPU based on 3rd generation Graphics Core Next (GCN) architecture

1. AMD in its technical documentation uses KB, which it defines as Kilobyte and as equal to 1024 bytes, and MB, which it defines as Megabyte and as equal to 1024 KB.
2. Single-precision performance is calculated from the base (or boost) core clock speed based on a FMA operation.

Mobile processors with 3D graphics

APU or Radeon Graphics branded

Sabine: "Llano" (2011)

• Fabrication 32 nm on GlobalFoundries SOI process
• Socket FS1
• Upgraded Stars (AMD 10h architecture) codenamed Husky CPU cores (K10.5) with no L3 cache, and with Redwood-class integrated graphics on die
• L1 Cache: 64 KB Data per core and 64 KB Instructions per core(BeaverCreek for the dual-core variants and WinterPark for the quad-core variants)
• Integrated PCIe 2.0 controller
• GPU: TeraScale 2
• Select models support Turbo Core technology for faster CPU operation when the thermal specification permits
• Support for 1.35 V DDR3L-1333 memory, in addition to regular 1.5 V DDR3 memory specified
• 2.5 GT/s UMI
• MMX, Enhanced 3DNow!, SSE, SSE2, SSE3, SSE4a, ABM, NX bit, AMD64, AMD-V
• PowerNow!

1. AMD in its technical documentation uses KB, which it defines as Kilobyte and as equal to 1024 bytes, and MB, which it defines as Megabyte and as equal to 1024 KB.
2. Single-precision performance is calculated from the base (or boost) core clock speed based on a FMA operation.

Comal: "Trinity" (2012)

• Fabrication 32 nm on GlobalFoundries SOI process
• Socket FS1r2, FP2
• Based on the Piledriver architecture
• L1 Cache: 16 KB Data per core and 64 KB Instructions per module
• GPU: TeraScale 3 (VLIW4)
• MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, SSE4a, AMD64, AMD-V, AES, CLMUL, AVX, AVX 1.1, XOP, FMA3, FMA4, F16C, ABM, BMI1, TBM, Turbo Core
• Memory support: 1.35 V DDR3L-1600 memory, in addition to regular 1.5 V DDR3 memory specified (Dual-channel)
• 2.5 GT/s UMI
• Transistors: 1.303 billion
• Die size: 246 mm²

1. AMD in its technical documentation uses KB, which it defines as Kilobyte and as equal to 1024 bytes, and MB, which it defines as Megabyte and as equal to 1024 KB.
2. Single-precision performance is calculated from the base (or boost) core clock speed based on a FMA operation.

1. Unified shader processors (USPs): Texture mapping units (TMUs): Render output units (ROPs). 1 CU (Compute Unit) = 64 USPs: 4 TMUs : 1 ROPs

"Richland" (2013)

• Fabrication 32 nm on GlobalFoundries SOI process
• Socket FS1r2, FP2
• Elite Performance APU.
• CPU: Piledriver architecture
  • L1 Cache: 16 KB Data per core and 64 KB Instructions per module
• GPU: TeraScale 3 (VLIW4)
• MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, SSE4a, AMD64, AMD-V, AES, CLMUL, AVX, AVX 1.1, XOP, FMA3, FMA4, F16C, ABM, BMI1, TBM, Turbo Core

1. AMD in its technical documentation uses KB, which it defines as Kilobyte and as equal to 1024 bytes, and MB, which it defines as Megabyte and as equal to 1024 KB.
2. Single-precision performance is calculated from the base (or boost) core clock speed based on a FMA operation.

1. Unified shader processors (USPs): Texture mapping units (TMUs): Render output units (ROPs). 1 CU (Compute Unit) = 64 USPs: 4 TMUs : 1 ROPs

"Kaveri" (2014)

• Fabrication 28 nm
• Socket FP3
• Up to 4 Steamroller x86 CPU cores with 4 MB of L2 cache.
• L1 Cache: 16 KB Data per core and 96 KB Instructions per module
• MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, SSE4a, AMD64, AMD-V, AES, CLMUL, AVX, AVX 1.1, XOP, FMA3, FMA4, F16C, ABM, BMI1, TBM, Turbo Core
• Three to eight Compute Units (CUs) based on Graphics Core Next (GCN) microarchitecture; 1 Compute Unit (CU) consists of 64 Unified Shader Processors : 4 Texture Mapping Units (TMUs) : 1 Render Output Unit (ROPs)
• AMD Heterogeneous System Architecture (HSA) 2.0
• SIP blocks: Unified Video Decoder, Video Coding Engine, TrueAudio
• Dual-channel (2x64-bit) DDR3 memory controller
• Integrated custom ARM Cortex-A5 co-processor with TrustZone Security Extensions

1. AMD in its technical documentation uses KB, which it defines as Kilobyte and as equal to 1024 bytes, and MB, which it defines as Megabyte and as equal to 1024 KB.
2. Single-precision performance is calculated from the base (or boost) core clock speed based on a FMA operation.

"Carrizo" (2015)

• Fabrication 28 nm
• Socket FP4
• Up to 4 Excavator x86 CPU cores
• L1 Cache: 32 KB Data per core and 96 KB Instructions per module
• MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, SSE4a, AMD64, AMD-V, AES, CLMUL, AVX, AVX 1.1, AVX2, XOP, FMA3, FMA4, F16C, ABM, BMI1, BMI2, TBM, RDRAND, Turbo Core
• GPU based on Graphics Core Next 1.2

1. AMD in its technical documentation uses KB, which it defines as Kilobyte and as equal to 1024 bytes, and MB, which it defines as Megabyte and as equal to 1024 KB.
2. Single-precision performance is calculated from the base (or boost) core clock speed based on a FMA operation.

"Bristol Ridge" (2016)

• Fabrication 28 nm
• Socket FP4
• Two or four "Excavator+" x86 CPU cores
• L1 Cache: 32 KB Data per core and 96 KB Instructions per module
• MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, SSE4a, AMD64, AMD-V, AES, CLMUL, AVX, AVX 1.1, AVX2, XOP, FMA3, FMA4, F16C, ABM, BMI1, BMI2, TBM, RDRAND, Turbo Core
• GPU based on Graphics Core Next 1.2 with VP9 decoding

1. AMD in its technical documentation uses KB, which it defines as Kilobyte and as equal to 1024 bytes, and MB, which it defines as Megabyte and as equal to 1024 KB.
2. Single-precision performance is calculated from the base (or boost) core clock speed based on a FMA operation.

"Raven Ridge" (2017)

• Fabrication 14 nm by GlobalFoundries
• Transistors: 4.94 billion
• Socket FP5
• Die size: 210 mm²
• Zen CPU cores
• MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, SSE4a, AMD64, AMD-V, AES, CLMUL, AVX, AVX 1.1, AVX2, FMA3, F16C, ABM, BMI1, BMI2, RDRAND, Turbo Core
• Fifth generation GCN-based GPU

• v
• t
• e

1. Unified shaders : Texture mapping units : Render output units and Compute units (CU)
2. Single precision performance is calculated from the base (or boost) core clock speed based on a FMA operation.

"Picasso" (2019)

• Fabrication 12 nm by GlobalFoundries
• Socket FP5
• Die size: 210 mm²
• Up to four Zen+ CPU cores
• MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, SSE4a, AMD64, AMD-V, AES, CLMUL, AVX, AVX 1.1, AVX2, FMA3, F16C, ABM, BMI1, BMI2, RDRAND, Turbo Core
• Dual-channel DDR4 memory controller
• Fifth generation GCN-based GPU

Common features of Ryzen 3000 notebook APUs:

• Socket: FP5.
• All the CPUs support DDR4-2400 in dual-channel mode.
• L1 cache: 96 KB (32 KB data + 64 KB instruction) per core.
• L2 cache: 512 KB per core.
• All the CPUs support 16 PCIe 3.0 lanes.
• Includes integrated GCN 5th generation GPU.
• Fabrication process: GlobalFoundries 12LP (14LP+).

• v
• t
• e

1. Core Complexes (CCX) × cores per CCX
2. Unified Shaders : Texture Mapping Units : Render Output Units and Compute Units (CU)
3. Single precision performance is calculated from the base (or boost) core clock speed based on a FMA operation.

1. ^ Model also available as PRO version, released April 8, 2019.

"Renoir" (2020)

• Fabrication 7 nm by TSMC
• Socket FP6
• Die size: 156 mm²
• 9.8 billion transistors on one single 7 nm monolithic die
• Up to eight Zen 2 CPU cores
• L1 cache: 64 KB (32 KB data + 32 KB instruction) per core.
• L2 cache: 512 KB per core.
• Fifth generation GCN-based GPU
• Memory support: DDR4-3200 or LPDDR4-4266 in dual-channel mode.
• All the CPUs support 16 PCIe 3.0 lanes.

U

• v
• t
• e

1. All of the iGPUs are branded as AMD Radeon Graphics.

1. Core Complexes (CCX) × cores per CCX
2. Unified shaders : texture mapping units : render output units and compute units (CU)
3. Single precision performance is calculated from the base (or boost) core clock speed based on a FMA operation.

H

• v
• t
• e

1. All of the iGPUs are branded as AMD Radeon Graphics.

1. Core Complexes (CCX) × cores per CCX
2. Unified shaders : texture mapping units : render output units and compute units (CU)
3. Single precision performance is calculated from the base (or boost) core clock speed based on a FMA operation.

"Lucienne" (2021)

• Fabrication 7 nm by TSMC
• Socket FP6
• Die size: 156 mm²
• 9.8 billion transistors on one single 7 nm monolithic die
• Up to eight Zen 2 CPU cores
• Fifth generation GCN-based GPU (7 nm Vega)

Common features of Ryzen 5000 notebook APUs:

• Socket: FP6.
• All the CPUs support DDR4-3200 or LPDDR4-4266 in dual-channel mode.
• L1 cache: 64 KB (32 KB data + 32 KB instruction) per core.
• L2 cache: 512 KB per core.
• All the CPUs support 16 PCIe 3.0 lanes.
• Includes integrated GCN 5th generation GPU.
• Fabrication process: TSMC 7FF.

• v
• t
• e

1. Core Complexes (CCX) × cores per CCX
2. Unified shaders : texture mapping units : render output units and compute units (CU)
3. Single precision performance is calculated from the base (or boost) core clock speed based on a FMA operation.

1. All of the iGPUs are branded as AMD Radeon Graphics.

"Cezanne" (2021)

• Fabrication 7 nm by TSMC
• Socket FP6
• Die size: 180 mm²
• Up to eight Zen 3 CPU cores
• L1 cache: 64 KB (32 KB data + 32 KB instruction) per core.
• L2 cache: 512 KB per core.
• Fifth generation GCN-based GPU
• Memory support: DDR4-3200 or LPDDR4-4266 in dual-channel mode.
• All the CPUs support 16 PCIe 3.0 lanes.

U

• v
• t
• e

1. All of the iGPUs are branded as AMD Radeon Graphics.

1. Core Complexes (CCX) × cores per CCX
2. Unified shaders : texture mapping units : render output units and compute units (CU)
3. Single precision performance is calculated from the base (or boost) core clock speed based on a FMA operation.

1. ^ Model also available as Pro version as 5450U, 5650U, 5850U, released on March 16, 2021.

H

• v
• t
• e

1. All of the iGPUs are branded as AMD Radeon Graphics.

1. Core Complexes (CCX) × cores per CCX
2. Unified shaders : texture mapping units : render output units and compute units (CU)
3. Single precision performance is calculated from the base (or boost) core clock speed based on a FMA operation.

"Barceló" (2022)

• Fabrication 7 nm by TSMC
• Socket FP6
• Die size: 180 mm²
• Up to eight Zen 3 CPU cores
• L1 cache: 64 KB (32 KB data + 32 KB instruction) per core.
• L2 cache: 512 KB per core.
• Fifth generation GCN-based GPU
• Memory support: DDR4-3200 or LPDDR4-4266 in dual-channel mode.
• All the CPUs support 16 PCIe 3.0 lanes.

• v
• t
• e

1. All of the iGPUs are branded as AMD Radeon Graphics.

1. Core Complexes (CCX) × cores per CCX
2. Unified shaders : texture mapping units : render output units and compute units (CU)
3. Single precision performance is calculated from the base (or boost) core clock speed based on a FMA operation.

1. ^ Model also available as Pro version as 5475U, 5675U, 5875U, released on April 19, 2022.
2. ^ Model also available as Chromebook optimized version as 5425C, 5625C, 5825C, released on May 5, 2022.

"Rembrandt" (2022)

• Fabrication 6 nm by TSMC
• Socket FP7
• Die size: 210 mm²
• Up to eight Zen 3+ CPU cores
• Second generation RDNA-based GPU

Common features of Ryzen 6000 notebook APUs:

• Socket: FP7, FP7r2.
• All the CPUs support DDR5-4800 or LPDDR5-6400 in dual-channel mode.
• L1 cache: 64 KB (32 KB data + 32 KB instruction) per core.
• L2 cache: 512 KB per core.
• All the CPUs support 16 PCIe 4.0 lanes.
• Native USB 4 (40Gbps) Ports: 2
• Native USB 3.2 Gen 2 (10Gbps) Ports: 2
• Includes integrated RDNA 2 GPU.
• Fabrication process: TSMC N6 FinFET.

• v
• t
• e

1. Core Complexes (CCX) × cores per CCX
2. Unified shaders : texture mapping units : render output units and compute units (CU)
3. Single precision performance is calculated from the base (or boost) core clock speed based on a FMA operation.

1. ^ Model also available as PRO version (6650U, 6650H, 6650HS, 6850U, 6850H, 6850HS, 6950H, 6950HS), released on April 19, 2022.

"Phoenix" (2023)

• Fabrication 4 nm by TSMC
• Up to eight Zen 4 CPU cores
• Dual-channel DDR5 or LPDDR5x memory controller
• RDNA3 iGPU
• XDNA accelerator

"Dragon Range" (2023)

• Fabrication 5 nm (CCD) and 6 nm (cIOD) by TSMC
• Up to sixteen Zen 4 CPU cores
• Dual-channel DDR5 memory controller
• Basic RDNA2 iGPU

Ultra-mobile APUs

Brazos: "Desna", "Ontario", "Zacate" (2011)

• Fabrication 40 nm by TSMC
• Socket FT1 (BGA-413)
• Based on the Bobcat microarchitecture
• L1 Cache: 32 KB Data per core and 32 KB Instructions per core
• MMX, SSE, SSE2, SSE3, SSSE3, SSE4a, ABM, NX bit, AMD64, AMD-V
• PowerNow!
• DirectX 11 integrated graphics with UVD 3.0
• Z-series denote Desna; C-series denote Ontario; and the E-series denotes Zacate
• 2.50 GT/s UMI (PCIe 1.0 ×4)