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== PAE Xeon only ==
== "Physical Address Extension " vs "Physical-Address Extension" ==

I wanted to change ] into ] because it is the correct English spelling ("an extension regarding the physical addresses", not a physical peculiarity of a more generic "Address Extension") and also used by the official documentation by AMD: http://support.amd.com/TechDocs/24593.pdf

Unfortunately Intel does it wrong and writes this term without dash. :-(

Perhaps we should at least mention this fact in the beginning of the article? --] (]) 13:04, 12 February 2016 (UTC)

: Please don't. Intel invented it, they get to name it. Windows follows the Intel usage, as does the Shanley book. AMD appears to be a distinct minority in their usage. There is no possible confusion anyway, so no need for a hyphen. ] (]) 17:17, 12 February 2016 (UTC)

: I see you similarly moved Page Size Extension. I'll be undoing that. ] (]) 18:22, 12 February 2016 (UTC)

: Damn it. Since the redirects have edit histories, now we have to go through "requested moves" to fix it. ''Perhaps'' you should have at least asked before taking it upon yourself to move PSE? ] (]) 19:19, 12 February 2016 (UTC)

:: Sorry for that. I didn't want to make confusion. :-/
:: But according to ] the spelling ''with'' hyphen would be the correct one if Intel wouldn't define it as a fixed term without hyphen, right?
⚫ :: --] (]) 10:55, 15 February 2016 (UTC)

:::So which of them is the "common term", as per ]? ] (]) 11:08, 15 February 2016 (UTC)

:::: I checked almost all of the references here (got tired of it after about #23). Out of that batch, AMD appears to be alone in using the hyphen. ] (]) 04:47, 16 February 2016 (UTC)

*'''Comment'''. I don't care one way or the other. "Physical-address extension" is better English, but I don't see "physical address extension" giving rise to confusion with "physical address-extension". It's a technical term. Complicating the issue is the title is capped ("Physical Address Extension"), and that means the article is about a proper noun. It is not just a generic "physical-address extension" but rather the particular PAE described by Intel. ] (]) 04:14, 16 February 2016 (UTC)

== according to Geoff Chappel", Microsoft may limit 32-bit versions of Windows to 4GB as a matter of its licensing policy ==

This was finally confirmed by Rusonnovich with Internals 6.
6th Edition came out in 2 parts; Book 1 & Book 2. Book 2 contains a fair bit of undocumented info not found elsewhere.


Page 320/321 lists physical memory support for all Windows versions, as on MSDN, AND the limiting factors, which are:
"Licensing on 64-bit; '''licensing, hardware support'', and driver compatibility '''on 32-bit''"
p320

''problematic client driver ecosystem led to the decision for client editions to
ignore physical memory that resides above 4 GB''', even though they can theoretically address it''
p321


It should be made clear the only IA-32 processor which supported Physical Address Extension as defined by Intel was Xeon. PAE requires BOTH 36 address registers AND 36bit data bus for RAM.
Exactly as Geoff Chappell said...:)
It wasn't much of a secret tbh because AMD64 platforms running XP already made great use of 4-8GB RAM: No pagefile required. :)
Great for servers.


All IA-32 processors had at most a 32bit data bus. 36 address registers only allows paging - it is not PAE support.
Coming from Managed Services (Deployment), published material often proves more reliable than say MSDN libraries which can be rather ambiguous.......


Only Xeon had 36bits for RAM. Xeon supported 8GB RAM total. The 8GB was split into 2x 4GB memory banks accessed one bank at a time. The 32bit + 4bit bus allowed a segment selector.
(Xeon was technically a 36bit CPU).


⚫ ] (]) 23:25, 10 May 2020 (UTC)
No idea how to include a link to source which is '''Microsoft Windows Internals (6th Edition), Part 2, pages 320 & 321,'''
As a wiki newbie so I apologise in advance for breaking any rules. :)


:No, as that's rubbish. Where's the definition of that per Intel? The article currently has it right ] - the chipset and motherboard etc have to also support 36 bit, which I know myself certainly some non-Xeons did. <span class="vcard"><span class="fn">]</span>; ]</span> 22:09, 1 September 2020 (UTC)


== First Linux kernel to support PAE ==


The section says 2.3.23 but under the old scheme odd numbers were development kernels (2.2 series was the release, 2.3 was concurrent and the development space for what would ship as 2.4). Would probably make sense to also mention which kernel was the first to ship with PAE, since no released distro would use a development kernel. --] (]) 03:44, 1 May 2022 (UTC)
I saw some discussion also over absolute maximum RAM limits allowed by Microsoft...?
The official maximum is 2TB, the limit doesn’t come from any implementation or hardware limitation, but because Microsoft will support only configurations it can test. The largest tested and supported memory configuration is currently 2TB. <!-- Template:Unsigned IP --><small class="autosigned">—&nbsp;Preceding ] comment added by ] (]) 18:53, 14 July 2016 (UTC)</small> <!--Autosigned by SineBot-->

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PAE Xeon only

It should be made clear the only IA-32 processor which supported Physical Address Extension as defined by Intel was Xeon. PAE requires BOTH 36 address registers AND 36bit data bus for RAM.

All IA-32 processors had at most a 32bit data bus. 36 address registers only allows paging - it is not PAE support.

Only Xeon had 36bits for RAM. Xeon supported 8GB RAM total. The 8GB was split into 2x 4GB memory banks accessed one bank at a time. The 32bit + 4bit bus allowed a segment selector. (Xeon was technically a 36bit CPU).

Onzite. (talk) 23:25, 10 May 2020 (UTC)

No, as that's rubbish. Where's the definition of that per Intel? The article currently has it right Physical Address Extension#Hardware support - the chipset and motherboard etc have to also support 36 bit, which I know myself certainly some non-Xeons did. Widefox; talk 22:09, 1 September 2020 (UTC)

First Linux kernel to support PAE

The section says 2.3.23 but under the old scheme odd numbers were development kernels (2.2 series was the release, 2.3 was concurrent and the development space for what would ship as 2.4). Would probably make sense to also mention which kernel was the first to ship with PAE, since no released distro would use a development kernel. --97.115.191.42 (talk) 03:44, 1 May 2022 (UTC)

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