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			== PAE Xeon only ==
	== according to Geoff Chappel", Microsoft may limit 32-bit versions of Windows to 4GB as a matter of its licensing policy ==

	This was finally confirmed by Rusonnovich with Internals 6.
	6th Edition came out in 2 parts; Book 1 & Book 2. Book 2 contains a fair bit of undocumented info not found elsewhere.


	Page 320/321 lists physical memory support for all Windows versions, as on MSDN, AND the limiting factors, which are:
	"Licensing on 64-bit; '''licensing, hardware support'', and driver compatibility '''on 32-bit''"
	p320

	''problematic client driver ecosystem led to the decision for client editions to
	ignore physical memory that resides above 4 GB''', even though they can theoretically address it''
	p321

	Exactly as Geoff Chappell said...:)
	It wasn't much of a secret tbh because AMD64 platforms running XP already made great use of 4-8GB RAM: No pagefile required. :)
	Great for servers.

	Coming from Managed Services (Deployment), published material often proves more reliable than say MSDN libraries which can be rather ambiguous.......


	No idea how to include a link to source which is '''Microsoft Windows Internals (6th Edition), Part 2, pages 320 & 321,'''
	As a wiki newbie so I apologise in advance for breaking any rules. :)



	I saw some discussion also over absolute maximum RAM limits allowed by Microsoft...?
	The official maximum is 2TB, the limit doesn’t come from any implementation or hardware limitation, but because Microsoft will support only configurations it can test. The largest tested and supported memory configuration is currently 2TB. <!-- Template:Unsigned IP --><small class="autosigned">— Preceding ] comment added by ] (]) 18:53, 14 July 2016 (UTC)</small> <!--Autosigned by SineBot-->

	== "offset within page" does not come from the page-table entry ==

	The phrase should surely be . <!-- Template:Unsigned IP --><small class="autosigned">— Preceding ] comment added by ] (]) 23:56, 12 October 2016 (UTC)</small> <!--Autosigned by SineBot-->

			It should be made clear the only IA-32 processor which supported Physical Address Extension as defined by Intel was Xeon. PAE requires BOTH 36 address registers AND 36bit data bus for RAM.
	: You are of course correct - and nice catch, that's been on the page for a long time. You can of course make the change yourself if you want. Be ] ! ] (]) 03:08, 13 October 2016 (UTC)

			All IA-32 processors had at most a 32bit data bus. 36 address registers only allows paging - it is not PAE support.
	== " they defined an enhanced version of PAE", How Can We Interpret this "Enhanced Version"? ==

			Only Xeon had 36bits for RAM. Xeon supported 8GB RAM total. The 8GB was split into 2x 4GB memory banks accessed one bank at a time. The 32bit + 4bit bus allowed a segment selector.
	Misplaced Pages.org always have a lot of ''invented'' words by a lot of so called ''famous'' ''professionals''. Maybe those are the prominent features of wiki articles. We read, we learn and we appreciate all the motivations around them all.
			(Xeon was technically a 36bit CPU).

			] (]) 23:25, 10 May 2020 (UTC)
	Paging scheme, which AMD64 architecture adopted, is similar with the scheme using in the PAE, and also further extended into an additional paging level. So this "enhanced", we could see at this point. But is it an enhanced version of PAE? In order to answer this question, we have to take a deeper look at what PAE really is!

			:No, as that's rubbish. Where's the definition of that per Intel? The article currently has it right ] - the chipset and motherboard etc have to also support 36 bit, which I know myself certainly some non-Xeons did. <span class="vcard"><span class="fn">]</span>; ]</span> 22:09, 1 September 2020 (UTC)
	PAE is short for Physical Address(ing) Extension, from 16-bit to 32-bit, we call it an expansion. But from 32-bit towards 36-bit and even more, we could only call it an extension. For this extension, we could ensure that the extended part is not easy to touch, in other words, the map between 32-bit and 36-bit is not easily and directly one-to-one mapped, but further taking advantage of paging capability. So PAE, is not an extension of Physical Address, but also an extension of paging found in Intel 80386.

			== First Linux kernel to support PAE ==
	Not we have to take a look at paging in AMD64, this is a partial-to-partial paging schema, 48-bit linear address towards to up to 48-bit physical address. Limited to AMD64 architecture, there is not extension, so paging in AMD64 is not an PAE enabled, just like another version of paging found in 80386, but designed for 64-bit computing. Without changing the current scheme, it is hard to page 48-bit or more linear address to physical address larger than what 48-bit address could represent. This ensures that there is no extension at all again.

			The section says 2.3.23 but under the old scheme odd numbers were development kernels (2.2 series was the release, 2.3 was concurrent and the development space for what would ship as 2.4). Would probably make sense to also mention which kernel was the first to ship with PAE, since no released distro would use a development kernel. --] (]) 03:44, 1 May 2022 (UTC)
	So "They defined an enhanced version of PAE" is logically wrong expression. We could make a little bit correction towards it like, they defined an enhanced version of paging scheme found in PAE. That would be much better. <!-- Template:Unsigned --><small class="autosigned">— Preceding ] comment added by ] (] • ]) 00:34, 15 October 2016 (UTC)</small> <!--Autosigned by SineBot-->

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PAE Xeon only

It should be made clear the only IA-32 processor which supported Physical Address Extension as defined by Intel was Xeon. PAE requires BOTH 36 address registers AND 36bit data bus for RAM.

All IA-32 processors had at most a 32bit data bus. 36 address registers only allows paging - it is not PAE support.

Only Xeon had 36bits for RAM. Xeon supported 8GB RAM total. The 8GB was split into 2x 4GB memory banks accessed one bank at a time. The 32bit + 4bit bus allowed a segment selector. (Xeon was technically a 36bit CPU).

Onzite. (talk) 23:25, 10 May 2020 (UTC)

No, as that's rubbish. Where's the definition of that per Intel? The article currently has it right Physical Address Extension#Hardware support - the chipset and motherboard etc have to also support 36 bit, which I know myself certainly some non-Xeons did. Widefox; talk 22:09, 1 September 2020 (UTC)

First Linux kernel to support PAE

The section says 2.3.23 but under the old scheme odd numbers were development kernels (2.2 series was the release, 2.3 was concurrent and the development space for what would ship as 2.4). Would probably make sense to also mention which kernel was the first to ship with PAE, since no released distro would use a development kernel. --97.115.191.42 (talk) 03:44, 1 May 2022 (UTC)

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