Talk:Physical Address Extension: Difference between revisions

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			== PAE Xeon only ==
	== "offset within page" does not come from the page-table entry ==

	The phrase should surely be . <!-- Template:Unsigned IP --><small class="autosigned">— Preceding ] comment added by ] (]) 23:56, 12 October 2016 (UTC)</small> <!--Autosigned by SineBot-->

	: You are of course correct - and nice catch, that's been on the page for a long time. You can of course make the change yourself if you want. Be ] ! ] (]) 03:08, 13 October 2016 (UTC)

			It should be made clear the only IA-32 processor which supported Physical Address Extension as defined by Intel was Xeon. PAE requires BOTH 36 address registers AND 36bit data bus for RAM.
	: Great, I agree with you, not "from the linear virtual address...", but ''from the linear address''. We could keep differentiating simplify linear addressing from virtual address, because the latter could also used to represents the former. <!-- Template:Unsigned --><small class="autosigned">— Preceding ] comment added by ] (] • ]) 00:44, 15 October 2016 (UTC)</small> <!--Autosigned by SineBot-->

			All IA-32 processors had at most a 32bit data bus. 36 address registers only allows paging - it is not PAE support.
	== " they defined an enhanced version of PAE", How Can We Interpret this "Enhanced Version"? ==

			Only Xeon had 36bits for RAM. Xeon supported 8GB RAM total. The 8GB was split into 2x 4GB memory banks accessed one bank at a time. The 32bit + 4bit bus allowed a segment selector.
	Misplaced Pages.org always have a lot of ''invented'' words by a lot of so called ''famous'' ''professionals''. Maybe those are the prominent features of wiki articles. We read, we learn and we appreciate all the motivations around them all.
			(Xeon was technically a 36bit CPU).

			] (]) 23:25, 10 May 2020 (UTC)
	Paging scheme, which AMD64 architecture adopted, is similar with the scheme using in the PAE, and also further extended into an additional paging level. So this "enhanced", we could see at this point. But is it an enhanced version of PAE? In order to answer this question, we have to take a deeper look at what PAE really is!

			:No, as that's rubbish. Where's the definition of that per Intel? The article currently has it right ] - the chipset and motherboard etc have to also support 36 bit, which I know myself certainly some non-Xeons did. <span class="vcard"><span class="fn">]</span>; ]</span> 22:09, 1 September 2020 (UTC)
	PAE is short for Physical Address(ing) Extension, from 16-bit to 32-bit, we call it an expansion. But from 32-bit towards 36-bit and even more, we could only call it an extension. For this extension, we could ensure that the extended part is not easy to touch, in other words, the map between 32-bit and 36-bit is not easily and directly one-to-one mapped, but further taking advantage of paging capability. So PAE, is not only an extension of Physical Address, but also an extension of paging found in Intel 80386.

			== First Linux kernel to support PAE ==
	Now we have to take a look at paging in AMD64, this is a partial-to-partial paging schema, 48-bit linear address towards to up to 48-bit physical address. Obviously, there is no extension, so paging in AMD64 is not an PAE enabled, but just like another version of paging found in 80386, designed for 64-bit computing. Without changing the current scheme, it is hard to page 48-bit or more linear address to physical address larger than what 48-bit address could represent. This ensures the presumption that there is no extension at all once again.

			The section says 2.3.23 but under the old scheme odd numbers were development kernels (2.2 series was the release, 2.3 was concurrent and the development space for what would ship as 2.4). Would probably make sense to also mention which kernel was the first to ship with PAE, since no released distro would use a development kernel. --] (]) 03:44, 1 May 2022 (UTC)
	So "They defined an enhanced version of PAE" is logically wrong. We could make a little bit correction towards it, i.e. '''they defined an enhanced version of paging scheme found in PAE'''. That would be much better. <!-- Template:Unsigned --><small class="autosigned">— Preceding ] comment added by ] (] • ]) 00:34, 15 October 2016 (UTC)</small> <!--Autosigned by SineBot-->

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PAE Xeon only

It should be made clear the only IA-32 processor which supported Physical Address Extension as defined by Intel was Xeon. PAE requires BOTH 36 address registers AND 36bit data bus for RAM.

All IA-32 processors had at most a 32bit data bus. 36 address registers only allows paging - it is not PAE support.

Only Xeon had 36bits for RAM. Xeon supported 8GB RAM total. The 8GB was split into 2x 4GB memory banks accessed one bank at a time. The 32bit + 4bit bus allowed a segment selector. (Xeon was technically a 36bit CPU).

Onzite. (talk) 23:25, 10 May 2020 (UTC)

No, as that's rubbish. Where's the definition of that per Intel? The article currently has it right Physical Address Extension#Hardware support - the chipset and motherboard etc have to also support 36 bit, which I know myself certainly some non-Xeons did. Widefox; talk 22:09, 1 September 2020 (UTC)

First Linux kernel to support PAE

The section says 2.3.23 but under the old scheme odd numbers were development kernels (2.2 series was the release, 2.3 was concurrent and the development space for what would ship as 2.4). Would probably make sense to also mention which kernel was the first to ship with PAE, since no released distro would use a development kernel. --97.115.191.42 (talk) 03:44, 1 May 2022 (UTC)

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