Talk:Physical Address Extension: Difference between revisions

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			== PAE Xeon only ==

			It should be made clear the only IA-32 processor which supported Physical Address Extension as defined by Intel was Xeon. PAE requires BOTH 36 address registers AND 36bit data bus for RAM.
	== "offset within page" does not come from the page-table entry ==

	The phrase should surely be . <!-- Template:Unsigned IP --><small class="autosigned">— Preceding ] comment added by ] (]) 23:56, 12 October 2016 (UTC)</small> <!--Autosigned by SineBot-->

	: You are of course correct - and nice catch, that's been on the page for a long time. You can of course make the change yourself if you want. Be ] ! ] (]) 03:08, 13 October 2016 (UTC)

	{{Done}}

	== As to the PAE kernel for Linux ==

	That is a long and old news that even though the processors, x86 or IA-32, lack support of PAE, could also be equipped with PAE kernel. As to the further information, one could retrieve such information from Linux kernel source, from http://www.kernel.org. <!-- Template:Unsigned IP --><small class="autosigned">— Preceding ] comment added by ] (]) 00:42, 9 May 2017 (UTC)</small> <!--Autosigned by SineBot-->

	:The only kernels that can run on a processor without PAE support are 1) kernels without PAE support and 2) kernels that check whether the hardware supports PAE, enables it if and only if present, ''and'', depending on whether PAE is enabled or not, use different code to manage page table entries.

			All IA-32 processors had at most a 32bit data bus. 36 address registers only allows paging - it is not PAE support.
	:If you look at the Linux kernel source, in {{mono\|arch/x86/include/asm/pgtable_32_types.h}}, you'll see a comment

			Only Xeon had 36bits for RAM. Xeon supported 8GB RAM total. The 8GB was split into 2x 4GB memory banks accessed one bank at a time. The 32bit + 4bit bus allowed a segment selector.
	/*
			(Xeon was technically a 36bit CPU).
	* The Linux x86 paging architecture is 'compile-time dual-mode', it
	* implements both the traditional 2-level x86 page tables and the
	* newer 3-level PAE-mode page tables.
	*/

			] (]) 23:25, 10 May 2020 (UTC)
	:and, in fact, whether the kernel uses pre-PAE or PAE page tables on 32-bit x86 processors is set at compile time, ''not'' determined at run time, so a kernel with PAE support will work only on a machine that supports PAE; a kernel without PAE support will work on a machine that supports PAE, but it won't use PAE and will only handle 4GB of physical memory.

			:No, as that's rubbish. Where's the definition of that per Intel? The article currently has it right ] - the chipset and motherboard etc have to also support 36 bit, which I know myself certainly some non-Xeons did. <span class="vcard"><span class="fn">]</span>; ]</span> 22:09, 1 September 2020 (UTC)
	:So, no, you can't run a PAE kernel on a processor that lacks PAE support; anybody who believes that it does either hasn't read the Linux kernel source or read it but didn't understand it. ] (]) 03:34, 9 May 2017 (UTC)

			== First Linux kernel to support PAE ==
	:: yeah, you are definitely correct! <!-- Template:Unsigned IP --><small class="autosigned">— Preceding ] comment added by ] (]) 12:50, 9 May 2017 (UTC)</small> <!--Autosigned by SineBot-->

			The section says 2.3.23 but under the old scheme odd numbers were development kernels (2.2 series was the release, 2.3 was concurrent and the development space for what would ship as 2.4). Would probably make sense to also mention which kernel was the first to ship with PAE, since no released distro would use a development kernel. --] (]) 03:44, 1 May 2022 (UTC)
	{{Done}}

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PAE Xeon only

It should be made clear the only IA-32 processor which supported Physical Address Extension as defined by Intel was Xeon. PAE requires BOTH 36 address registers AND 36bit data bus for RAM.

All IA-32 processors had at most a 32bit data bus. 36 address registers only allows paging - it is not PAE support.

Only Xeon had 36bits for RAM. Xeon supported 8GB RAM total. The 8GB was split into 2x 4GB memory banks accessed one bank at a time. The 32bit + 4bit bus allowed a segment selector. (Xeon was technically a 36bit CPU).

Onzite. (talk) 23:25, 10 May 2020 (UTC)

No, as that's rubbish. Where's the definition of that per Intel? The article currently has it right Physical Address Extension#Hardware support - the chipset and motherboard etc have to also support 36 bit, which I know myself certainly some non-Xeons did. Widefox; talk 22:09, 1 September 2020 (UTC)

First Linux kernel to support PAE

The section says 2.3.23 but under the old scheme odd numbers were development kernels (2.2 series was the release, 2.3 was concurrent and the development space for what would ship as 2.4). Would probably make sense to also mention which kernel was the first to ship with PAE, since no released distro would use a development kernel. --97.115.191.42 (talk) 03:44, 1 May 2022 (UTC)

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