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	The '''Efficeon''' processor is ]'s second-generation ] ] design which employs a software engine to convert code written for ] processors to the native ] of the chip (Code Morphing Software, aka CMS). Like its predecessor, the ] (a ] VLIW architecture), Efficeon stresses computational efficiency, low power consumption, and a low thermal footprint.
			The '''Efficeon''' (stylized as '''efficēon''') processor is ]'s second-generation ] ] design released in 2004 which employs a software engine ] (CMS) to convert code written for ] processors to the native ] of the chip. Like its predecessor, the ] (a ] VLIW architecture), Efficeon stresses computational efficiency, low power consumption, and a low thermal footprint.

			==Processor==
	Efficeon most closely mirrors the feature set of ] ] processors, although, like ] ] processors, it supports a fully integrated ], a ] IO bus, and the ], or no-execute ] extension to ]. ] support is available starting with CMS version 6.0.4.
			Efficeon most closely mirrors the feature set of ] ] processors, although, like ] ] processors, it supports a fully integrated ], a ] IO bus, and the ], or no-execute ] extension to ]. ] support is available starting with CMS version 6.0.4.

	Efficeon's computational performance relative to mobile CPUs like the ] ] is thought to be lower, although little appears to be published about the relative performance of these competing processors.		Efficeon's computational performance relative to mobile CPUs like the ] ] is thought to be lower, although little appears to be published about the relative performance of these competing processors.

	Efficeon came in two ] types: a 783- and a 592-contact ]. Its power consumption is moderate (with some consuming as little as 3 watts at 1 GHz and 7 watts at 1.5 GHz), so it can be passively cooled.		Efficeon came in two ] types: a 783- and a 592-contact ] (BGA). Its power consumption is moderate (with some consuming as little as 3 watts at 1 GHz and 7 watts at 1.5 GHz), so it can be passively cooled.

	Two generations of this chip were produced. The first generation (TM8600) was manufactured using a ] 0.13 micrometre process and produced at speeds up to 1.2 ]. The second generation (TM8800 and TM8820) was manufactured using a ] 90 nm process and produced at speeds ranging from 1 GHz to 1.7 GHz.		Two generations of this chip were produced. The first generation (TM8600) was manufactured using a ] 0.13 micrometre process and produced at speeds up to 1.2 ]. The second generation (TM8800 and TM8820) was manufactured using a ] 90 nm process and produced at speeds ranging from 1 GHz to 1.7 GHz.

	Internally, the Efficeon has two ]s, two load/store/add units, two execute units, two ]/]/]/] units, one ] unit, one alias unit, and one control unit. The VLIW core can execute a 256-bit VLIW instruction per cycle, which is called a molecule and has room to store eight 32-bit instructions (called atoms) per cycle.		Internally, the Efficeon has two ]s, two load/store/add units, two execute units, two ]/]/]/] units, one ], one alias unit, and one control unit. The VLIW core can execute a 256-bit VLIW instruction per cycle, which is called a molecule, and has room to store eight 32-bit instructions (called atoms) per cycle.

	The Efficeon has a 128 KB L1 instruction cache, a 64 KB L1 data cache and a 1 MB L2 cache. All caches are on die.		The Efficeon has a 128 KB L1 instruction cache, a 64 KB L1 data cache and a 1 MB L2 cache. All caches are on die.

			Additionally, the Efficeon CMS (code morphing software) reserves a small portion of main memory (typically 32 MB) for its translation cache of dynamically translated x86 instructions.









	CONTENTS


	• ABSTRACT

	• INTRODUCTION

	• OVERVIEW

	• ARCHITECTURE

	• FEATURES AND BENEFITS

	• SPECIFICATION

	• PARTNER TECHNOLOGIES

	• APPLICATIONS

	• DISADVANTAGES

	• CONCLUSION




	ABSTRACT

	The Transmeta™ Efficeon™ processor represents a new breakthrough in Efficient Computing. Built upon a revolutionary but proven hardware/software architecture, the Efficeon processor is an intelligent, sensible alternative to competitive offerings.

	Efficeon offers freedom of choice for those seeking best-in-class chip set components and gives product vendors the ability to build in added value, functionality, security, comfort, reliability and cost-savings.

	The processor ushers in a new era of efficient computing for users of ultra-portable and mainstream notebook computers and enables innovative new devices such as tablet PCs, ultra-personal computers, silent desktop computers, blade servers and embedded systems.




























	INTRODUCTION


	EFFICEON PROCESSOR


	The Transmeta family of Efficeon processors are different from every other processor available today. On the surface, the Efficeon processor runs all x86-based operating systems and software applications just like other x86 processors. Under the hood, the architecture driving the Efficeon processor provides a level of engineering and optimization that surpasses other x86 architectures.

	Transmeta, the leader in efficient computing, has rethought microprocessor design from the ground up.

	With the next-generation Efficeon family of processors, Transmeta ushers in a new era of energy efficient computing. The Efficeon processor, designed from the start to increase performance and responsiveness, addresses the ever-growing demand for power-efficient x86 solutions.

	With features including three new high-performance I/O interfaces, a faster engine with wider execution paths, a fully re-engineered instruction set, and higher frequency capabilities, the Efficeon processor is built to deliver more performance than the Crusoe processor while maintaining Transmeta’s proven energy efficiency.







	OVERVIEW


	A new breakthrough in Efficient Computing. Built on revolutionary but proven hardware/software architecture. Offers freedom of choice for those seeking best-in-class chip set components and gives product vendors the ability to build in added value, functionality, security, comfort, reliability and cost-savings.

	Ushers in a new era of efficient computing for users of ultra-portable and mainstream notebook computers and enables innovative new device.

	Built upon Fujitsu’s next-generation 90nm silicon technology featuring transistors with an industry-leading length of 40nm, delivering another major leap forward in performance and power efficiency.

	Offering an unmatched combination of power efficiency, design flexibility, performance-on-demand and low cost.















	ARCHITECTURE

	The Transmeta™ Efficeon™ processor represents a new breakthrough in Efficient Computing. Built upon a revolutionary but proven hardware/software architecture, the Efficeon processor is an intelligent, sensible alternative to competitive offerings. Efficeon offers freedom of choice for those seeking best-in-class chip set components and gives product vendors the ability to build in added value, functionality, security, comfort, reliability and cost-savings.

	The processor ushers in a new era of efficient computing for users of ultra-portable and mainstream notebook computers and enables innovative new devices such as tablet PCs, ultra-personal computers, silent desktop computers, blade serversand embedded systems.






	High Performance 8 Instruction Issue, 256-Bit VLIW Engine


	The Transmeta™ Efficeon™ processor is designed to address the ever-growing demand for power-efficient x86 solutions.

	To maximize performance and responsiveness, the Efficeon processor features a state-of-the-art 256-bit-wide VLIW (Very Long Instruction Word) engine that can issue up to 8 instructions per clock cycle. A large 1MB L2 cache and support for SSE & SSE2 instructions help make for a compelling multimedia experience. This hardware engine is the heart of the Efficeon processor.
















	This hardware engine processes instructions like a conventional processor, but runs a custom, efficient instruction set. Transmeta's proprietary Code Morphing™ Software (CMS) is the software component of the Efficeon processor. CMS dynamically optimizes and translates x86 instructions into VLIW native code that the VLIW hardware engine can process.

	This unique combination of hardware and software allows the processor to be more streamlined and adds intelligence to the Efficeon processor not found in other x86 microprocessors. Efficeon's software manages power consumption and heat, providing a user-satisfying performance that is competitive with leading mobile solutions in its class.



	Features/Benefits

	High Performance, 8 Instruction Issue, 256-Bit VLIW Engine

	1. Up to eight instructions issued per clock cycle
	2. SSE and SSE2 Support. The addition of these extensions enables multimedia applications to run up to 80% faster per clock cycle than previous generation processors from Transmeta.
	3. Up to 50% improvement in performance in integer applications over previous generation processors from Transmeta
	4. Large 1MB L2 cache improves processor performance





	Advanced Code Morphing™ Software


	With the new Code Morphing Software (CMS) for the Transmeta™ Efficeon™ processor, Transmeta extends its leadership in power management, offering a solution that provides high performance while consuming less power for the same work. The result is a highly efficient x86 solution suitable for notebook computers, Tablet PC´s and many other applications where low power x86 processors are desirable.


	The Transmeta software layer was given the name Code Morphing becauseof the way it dynamically morphs x86 instructions into VLIW instructions. This provides x86 software with the impressionthat it is being run on native x86 hardware. Typically, the most complex part of a processor's job — determining what instructions to execute and when — is implemented with additional hardware logic transistors.


	Transmeta accomplishes the very same translation in software, eliminating the need for additional hardware logic transistors. Fewer transistors equates to less heat dissipation and a cooler-running processor.





	Since the x86 instruction set architecture is decoupled from the underlying processor hardware, the underlying hardware can be changed radically without affecting legacy x86 software, allowing Transmeta to innovate the hardware more than is typically possible. This also means that each new processor design only requires a new version of CMS to translate x86instructions to the new processor's native instruction set.

	This new generation of Code Morphing Software leverages the Transmeta Efficeon processor's 256-bit VLIW advances and its ability to issue up to 8 instructions per clock cycle — double the number of instructions that could be issued with previous processors. This combination of technologies is key to reducing power consumption.





	Features/Benefits


	Advanced Code Morphing Software


	1. Improves performance and responsiveness over 1st generation Transmeta Crusoe technology

	2. New generation Code Morphing Software technology leverages 256-bit VLIW hardware advances

	3. Unique software-based architecture is key to reducing power consumption and enabling future scalability and flexibility

	4. Enables quick, low cost improvements to performance and power consumption with updates of Code Morphing Software.
























	Integrated architecture:


	Transmeta™ continues to innovate by incorporating full Northbridge core logic functionality directly onto the Efficeon™ processor die. This level of integration provides many benefits including reduced chip count, reduced overall board space, increased energy efficiency, and cost savings by removing the need for additional Northbridge chips.



















	Three high speed I/O interfaces allow the Transmeta Efficeon to achieve more work per clock: a DDR-400 memory interface, a point-to-point, low-voltage HyperTransport™ interconnect, and an AGP 4X graphics interface. By integrating these interfaces, the Transmeta Efficeon processor is able to achieve more work per clock, which results in greater energy efficiency, better I/O throughput and longer battery life for mobile computer users.



	Features/Benefits

	Fully Integrated Northbridge Core Logic

	1. On-chip Double Date Rate 400 (DDR-400) SDRAM memory interface. DDR-400 SDRAM substantially increases throughput over earlier DDR-266 interface.

	2. Integrated AGP 2.0 compliant graphics interface for industry standard, high performance graphics solutions at 1X, 2X & 4X data rates

	3. On-chip 400 MHz HyperTransport interface, 8-bits wide in each direction, provides 12x the I/O throughput compared to 32-bit, 33 MHz PCI.

	4. On-chip industry standard Low Pin Count (LPC) bus, allowing it to communicate with new, high-density LPC Flash memories.

	5. Full support for ECC in L2 cache and northbridge memory controller enables expansion into the server market.






	AntiVirusNX™ Technology


	In response to the escalating threat of computer virus attacks, Transmeta has introduced a new feature on Efficeon processors - called AntiVirusNX - that can detect common viruses and render them harmless for Efficeon-based computers. AntiVirusNX works in conjunction with Microsoft's Data Execution Protection (DEP) technology in Windows XP Service Pack 2 to detect and prevent attempts by attackers to overflow memory buffers with malicious virus content.

	AntiVirusNX represents a significant deterrent to the ever increasing threat of computer viruses, many of which (including the recent Sasser, Blaster, Code Red, Bugbear worms) have leveraged buffer overflows as a means of entry into a computer operating system.

	Some of the most devastating attacks, including numerous worms, as well as many other malicious programs, attack computers by attempting to insert and execute code from data regions of system memory. The Data Execution Protection (DEP) feature in Windows XP Service Pack 2 leverages the Efficeon processor's AntiVirusNX technology to stop this malicious code immediately if it attempts to execute and thereby infect the computer. This combination offers significant improvements against software worms and viruses, providing enhanced security and safer computing.












	How Buffer Overflows Spread Viruses

	Buffer overflows in software programs account for a large number of computer intrusions. Buffer overflows occur when the data intended for software is actually larger than the memory area set aside for that data.
	An analogy would be pouring the entire contents of a pitcher into a glass; once the glass is full, the excess liquid pours over the side. Malicious code hidden in the overflow is then executed by the computer.







	Transmeta AntiVirusNX and Microsoft (DEP)

	The combination of Data Execution Protection (DEP) and AntiVirusNX technology marks all program memory locations as non-executable unless the location explicitly contains executable code. It does this by relying on the
	Efficeon processor to mark memory with an attribute indicating that code should not be executed from that memory.

	Transmeta AntivirusNX Technology:

	• Works closely with DEP to identify code entering an Efficeon processor after a buffer overflow occurs.

	• Shields Efficeon processors from buffer overflow vulnerabilities by marking the code as non-executable.

	• Complements 3rd party anti-virus software. For full protection, users are strongly recommended to install and regularly update 3rd-party anti-virus software to enhance overall system security.













	Enhanced LongRun™ Dynamic Power/Thermal Management


	LongRun power management technology provides Code Morphing software with the ability to adjust the Efficeon processor core operating voltage and clock frequency dynamically, depending on the demands placed on the processor by software. Because power varies linearly with clock speed and by the square of voltage, adjusting both processor voltage and clock frequency can produce cubic reductions in power consumption, whereas conventional processors can adjust power linearly only by adjusting the effective operating frequency.

	LongRun power management policies are implemented within Code Morphing software, and can detect different workload scenarios based on runtime performance information, and then exploit these by adapting processor power usage accordingly. This ensures the processor delivers high performance when necessary and conserves power when demand on the processor is low.





	Morphing software monitors the Efficeon processor and dynamically switches between these points as runtime conditions change. If no idle time is detected during a workload, the frequency/voltage point is incremented (if possible).
	If idle time is detected, LongRun may decide that performance is being wasted and decrement the frequency/voltage level.

	LongRun also works in conjunction with the industry standard ACPI (Advanced Configuration and Power Interface) specification — when the frequency and voltage scaling hits microarchitecture boundaries, Crusoe transparently switches over to traditional power models allowing policies such as ACPI to handle power management.

	Features/Benefits

	Enhanced LongRun Dynamic Power Management

	• Enables longer battery life by continuously adjusting operating frequency and voltage to match the performance requirements of application workloads

	• More efficient than typical duty cycle clock throttling power management schemes

	Enhanced LongRun Thermal Management

	• Maximizes performance within a thermal envelope

	• Low thermal characteristics enable fanless designs for quieter and more reliable systems.




	FEATURES AND BENEFIS


	Feature Benefits
	Enhanced Hardware Engine High Performance, 8 Instruction Issue, 256-bit Engine Up to eight instructions issued per clock cycle.
	SSE and SSE2 Support. The addition of these extensions enables multimedia applications to run up to 80% faster per clock cycle than previous generation processors from Transmeta.
	Up to 50% improvement in performance in integer applications over previous generation processors from Transmeta.
	x86 Microprocessor with Large 1 MB High Speed L2 Cache Improved processor performance.
	Reduces potential for cache misses.
	Reduces need to access main memory.
	2nd Generation Software Engine Advanced Code Morphing™ Software (CMS) Improves performance and responsiveness over 1st generation Transmeta Crusoe technology.
	New generation Code Morphing Software technology leverages 256-bit VLIW hardware advance.
	Unique software based architecture is key to reducing power consumption and enabling future scalability and flexibility.
	Enables quick, low cost improvements to performance and power consumption with updates of Code Morphing Software.
	Highly Integrated Architecture Fully Integrated Northbridge Functionality Designed specifically for the needs of mobile applications:
	Board space is a premium for the thinner and lighter notebooks
	Battery life is paramount
	Reduced chip count is key to reducing manufacturing complexity and costs
	Full integrated Northbridge is the key to:
	Reduced board space
	Reduced power consumption
	Reduced chip count
	Improved memory performance
	On-Chip AGP 2.0 Compliant Graphics Interface For industry standard, high performance graphics solutions at 1X, 2X and 4X data rates.
	Flexibility to support all standard mobile graphics solutions.
	Provides customers with a wide range of options for innovation.
	On-Chip DDR400 memory controller with Support for ECC Memory Supports 266, 333, and 400MHz DDR to allow best price/performance options.
	Substantially increases throughput over earlier DDR-266 interfaces
	Supports highest performance memory available for thin and light notebooks and tablet PC mobile platforms.
	Provides very low latency access into main memory, improving memory performance.
	Reduces power consumption.
	Error Correction Code (ECC) is a great option for high density or high energy efficient applications, enabling expansion into the server market.
	On-chip 400Mhz HyperTransport™ Point-to-Point, Low-Voltage Differential Signal (LVDS) Interface Provides 12x the I/O throughput compared to 32-bit, 33MHz PCI.
	Provides high-speed, high bandwidth, energy efficient link to I/O devices using fewer pins.
	Supports transfer of time-dependent data for fluid playback of multimedia video and audio.
	Asymmetrical links scale in speed, width, and direction providing designers flexibility between power savings and performance.
	Industry-wide support of HyperTransport component.
	On-chip Industry Standard Low Pin Count (LPC) Bus Provides design flexibility by allowing a dedicated flash to be connected directly to the processor.
	Allows for communication with new, high-density LPC Flash memories.
	Ultra Low Power Design Enhanced LongRun™ Dynamic Power Management Technology Enables longer battery life by continuously adjusting operating frequency and voltage to match the performance requirements of application workloads.
	More efficient than typical duty cycle clock throttling power management schemes.
	Enhanced LongRun Advanced Thermal Management Technology Maximizes performance within a thermal envelope.
	Low thermal characteristics enable fanless designs for quieter and more reliable systems.





















	SPECIFICATION






	Frequency 1.1 GHz Up to 1.7 GHz Up to 1.4 GHz 1.0 GHz - 1.1 GHz
	L1 Instruction Cache 128 KB 128 KB 128 KB 128 KB
	L1 Data Cache 64 KB 64 KB 64 KB 64 KB
	L2 Write-Back Cache 1 MB 1 MB 1 MB 1 MB
	VLIW Processor Engine 256-bit 256-bit 256-bit 256-bit
	Instructions Issued Per Clock Cycle Up to 8 Up to 8 Up to 8 Up to 8
	Fully Integrated Northbridge Yes Yes Yes Yes
	Integrated DDR SDRAM Memory Support DDR-266, 333 DDR-266, 333 DDR-266, 333 DDR-266, 333
	Support for ECC Memory Yes Yes Yes Yes
	Integrated Graphics Interface AGP 1X, 2X, and 4X AGP 1X, 2X, and 4X AGP 1X, 2X, and 4X AGP 1X, 2X, and 4X
	System Bus HyperTransport™ HyperTransport HyperTransport HyperTransport
	System Bus Speed 400 MHz 400 MHz 400 MHz 400 MHz
	Aggregate I/O Total Bandwidth 1.6 GB/s 1.6 GB/s 1.6 GB/s 1.6 GB/s
	Integrated Low Pin Count Bus (LPC) Yes Yes Yes Yes
	Multimedia Instruction Support MMX, SSE-SSE3 MMX, SSE-SSE3 MMX, SSE-SSE3 MMX, SSE-SSE2
	Full x86 Software and OS Compatibility Yes Yes Yes Yes
	Enhanced LongRun™ Power Management Yes Yes Yes Yes
	Enhanced LongRun Thermal Management Yes Yes Yes Yes
	Max Temperature Up to 100°C Tj Up to 100C Tj Up to 100C Tj Up to 100C Tj
	Process Geometry Fujitsu 90nm Fujitsu 90nm Fujitsu 90nm TSMC 130nm
	Package Size 21mm x 21mm 29mm x 29mm 21mm x 21mm 21mm x 21mm
	Package 592-pin OBGA
	0.8mm ball pitch 783-pin OBGA
	1mm ball pitch 592-pin OBGA
	0.8mm ball pitch 783-pin OBGA
	1mm ball pitch

	PRODUCTS

	LongRun2 Technologies
	Transistor leakage is becoming an increasing problem as semiconductor technology scales to smaller dimensions. Industry experts have called transistor leakage one of the fundamental challenges to Moore's Law of technology scaling. Leakage problems are expected to get progressively worse as the industry scales to 90nm and 65nm transistors. Leakage power could easily dominate total chip power and prevent low power standby operation if not controlled.
	Transmeta's advanced LongRun2 technologies may be used to improve semiconductor devices by reducing total chip power, reducing standby power, reducing burn-in power, and potentially improving chip performance and reducing manufacturing costs. LongRun2 technologies build upon Transmeta's first generation LongRun power management technology, which pioneered the dynamic adjustment of MHz and voltage, hundreds of times per second, to reduce power consumption.
	LongRun2 technologies use Transmeta's innovative new approach for dynamically adjusting transistor threshold voltages to control transistor leakage. This dynamic control reduces leakage caused by changes in runtime conditions, such as voltage and temperature, which are not predetermined when the chip is manufactured.














	PARTNER TECNOLOGIES





























	APPLICATIONS

	a)NOTE BOOKS

	The unique architecture of Transmeta processors offers advantages over standard hardware-only processors, and that's why these leading manufacturers have chosen it. In addition to delivering new versions of processors on advanced processes, Transmeta is the only microprocessor company able to provide software upgrades to the processor that offer additional performance and power savings.
	This diverse lineup of the Transmeta based products represents a real innovation in the mobile computing market. Transmeta processors have been chosen by some of the industry's most creative companies for their longer, lighter and cooler designs.

	b)TABLET PCS:

	The Tablet PC is designed to operate anywhere without the restriction of a keyboard and mouse. Exciting Ink technology allows users to write directly on the screen with a pen although keyboard and mouse can be used if required.
	Much more versatile than your laptop and just as powerful as the PC on your desk top, the Tablet PC is the next step in the evolution of the personal computer. Now you can take your office anywhere, bring your business to your customers and connect to the rest of the world without wires.

	c)THIN CLIENTS:

	The thin client, differentiated from desktop computers by a smaller form factor and the removal of all moving parts (disk drive, fan, etc), is designed specifically for server-based computing. In a server-based environment, all applications for an individual user run on the server. In addition, all desktop management is centralized to the server, allowing the IT manager to focus on a few servers rather than thousands of desktop computers scattered over a wide area. This centralized approach provides IT managers with the ability to easily deploy applications to thousands of thin client users at the same time.

	The centralized application deployment utilized in server based computing with thin clients increases resource efficiency and drastically reduces the overhead associated with application installation and upgrades. Because all data is centrally located on a server, data is better protected from the catastrophes, viruses, and data theft that plague non-centralized operations. The solid state design of the thin client offers high reliability, helps lower ownership costs and extends product life.

	d)UPCS:

	The Ultra-Personal Computer (UPC) — a new computing category enabled by Transmeta processors — is a high-performance, full-featured personal computer that delivers the functionality of a desktop computer and the features of a laptop computer in the size of a handheld PDA.
	Industry standard components and connectivity features differentiate UPCs from other handheld devices. UPCs are designed to run full x86 desktop operating systems and applications, including Microsoft® Windows® XP Professional and Home Edition, giving users application independence and the freedom to use their data with the software of their choice.
	By consolidating computers and data into a single UPC, users can dramatically simplify or even eliminate the synchronization between multiple devices. This allows companies to benefit from increased productivity and reduced IT maintenance overhead while providing users with seamless portability of their data and multimedia content.

	For a computer to earn the UPC designation, it must not only adhere to performance and compatibility requirements, it must fit into a standard jacket pocket. This requirement has placed severe limitations upon electronic and component manufacturers, especially in the areas of processing. For Transmeta, this was never a concern due to the minimal footprint, low power consumption and reduced thermal dissipation of Transmeta processors.
	The goal of the UPC is simple: to create a practical, functional computer capable of running Windows XP and standard desktop applications that fits in the palm of the hand. To that end, Transmeta is working closely with hardware and software partners to ensure the success of the UPC market.

	e)SERVERS:

	Transmeta Corporation's entrance to the server market was simpler than expected. Thanks to the innovative designs of up-and-coming server companies, the power saving benefits of Crusoe and Efficeon processors are felt in an entirely new market.

	Since the Internet's aggressive rise in 1998, the proliferation of data centers, or "server farms" has increased dramatically. Considering the large volume of electricity required to power these data centers and the rising cost of energy in some parts of our nation, it was time for new technologies to come together and improve the market condition.

	When Data Centers purchase hardware for their facilities they traditionally use a profitability matrix based on the following rule: Performance/Per Watt/Per Cubic Foot. In simple terms this means they must squeeze as much processing power out of their two most limited resources — space and power. With the introduction of low power and high density Crusoe based servers these operators can now experience scores beyond anything the market has yet seen and in turn improve their bottom line profitability.


	f)DESKTOPS:

	The age of the noisy desktop computer is gone. Consumers want quiet computers that can be placed in alternative living spaces in their homes such as living rooms and kitchens. This requires a new kind of processor, one that can operate without the need for noisy fans. The Transmeta Crusoe and Efficeon processors have been designed explicitly to be run without cooling. By removing the need for fans and large heat sinks, computers can be built to use less energy, make less noise, and to take up less desktop space.

	g)WORKSTATIONS:

	Advanced cluster workstations remove the costs and infrastructure associated with traditional cluster servers while providing the necessary processing power to solve complex computational problems. By removing server cluster complexity and assembly time, cluster workstations are self contained, provide simple and easy-to-use features and can be quickly moved to and used in office or laboratory environments where standard wall outlets are located. Best of all, since they are built around industry standards and use standard software libraries, they can be configured to your needs.

	h)EMBEDDED DEVICES:

	Transmeta, the leader in efficient computing, offers a line of low power, high-performance processors designed to meet the unique requirements of embedded applications. The Transmeta™ Crusoe™ is an energy efficient processor built upon innovative technology that provides embedded devices a performance per watt ratio that is unmatched by any other x86-based processor in its class.


	Available in a variety of low power versions, the Transmeta Crusoe processor is ideal for applications that require high performance processing within small and thermally constrained environments. Its inherently energy efficient design allows gigahertz processor speeds without the need for active cooling and external CPU fans. Integrated power management technology further enhances efficiency by dynamically scaling both processor frequency and voltage according to the instantaneous demands of the computer system.
	Transmeta Crusoe and Crusoe SE processors are designed for embedded applications in the areas of office automation, networking/communications, storage, server-based computing, science and medicine, transportation, automotive/telematics, and industrial automation. Some example devices in these markets include: thin clients, blade servers, printers and copiers, point-of-sale, smart displays, hand held and portable consumer devices, ultra-personal computers, set-top boxes and many other applications.

	i)SINGLE BOARD COMPUTERS:

	Transmeta, the leader in efficient computing, markets a line of energy efficient, high-performance processors designed to meet the unique requirements of embedded applications.
	Transmeta Efficeon™ and Crusoe™ microprocessors are built upon innovative technologies that provide embedded devices full x86 compatibility within a performance per watt ratio that is unmatched by any other x86-based processor in its class. Both processors combine the processor and Northbridge functionality into a single integrated circuit, creating a single package that reduces board space by eliminating the need for a dedicated Northbridge chip. New versions of the processors further increase board space by reducing the 29mm x 29mm and 32.5mm x 25mm
	package sizes to a much smaller 21mm x 21mm package size — a savings of up to 48 percent!


	Available in a variety of low power ratings, Transmeta Efficeon & Crusoe processors are ideal for applications requiring high performance processing within small and thermally constrained environment without the need for active cooling fans. Integrated LongRun™ power management technology further enhances efficiency by dynamically scaling both processor frequency and voltage according to the instantaneous demands of the computer system.



























	DIS ADVANTAGES:

	Despite such features, Transmeta over the past few years has been hampered by costly delays and fierce competition from larger competitors such as Intel Corp. and Advanced Micro Devices Inc.
	For Transmeta, the company's past optimistic predictions have outstripped reality. The company has reported annual losses since the company's launch in 2000, and for most of its history, the company's pro-forma and net losses for each quarter have outstripped its revenues. During that time, the company's Crusoe processor has been positioned to a number of market segments, including notebooks, handhelds, and the embedded processor market.
	Not as high spec as other pc's .And it is rather large and ugle.
	Efficeon TM8800 - 1.2 GHz - 256 MB ... Disadvantages: slow under a lot of strain,
	The major disadvantage of VLIW is the loss of binary. code compatibility ... TM8800
	NX (Non Executable flag).

	Are there disadvantages?

	Yes, some. Any application that uses self-modifying code will likely have to be rewritten to ensure that its method of memory allocation and management doesn't render its modified codebase NX-flagged. One egregious self-modifier, according to several of my coder colleagues, is XFree86 - the freeware X Windows suite. It utilizes self-modifying code inside malloc()-ed ranges, so I'm not sure what'll need to be done to fix that. Also, the coder will lose some flexibility due to the need to pre-plan which memory ranges contain code and which contain data.





	Are there other ways of doing this?

	Sure. One method some architectures use is to have physically separate code and data memory ranges. This is even more sure, but is of course highly demanding of resources, and wasteful of them to boot.

	The Efficeon processor is Transmeta's second-generation 256-bit VLIW design which employs a software engine to convert code written for x86 processors to the native instruction set of the chip. Like its predecessor, the Transmeta Crusoe (a 128-bit VLIW architecture), Efficeon stresses computational efficiency, low power consumption, and a low thermal footprint.

	Efficeon most closely mirrors the feature set of Intel Pentium 4 processors, although, like AMD Opteron processors, it supports a fully integrated memory controller, a HyperTransport IO bus, and the NX bit, or no-execute, AMD64 x86 extension.

	Efficeon's computational performance relative to mobile CPUs like the Intel Pentium M is thought to be lower, although little appears to be published about the relative performance of these competing processors.

	Efficeon comes in two package types: a 783 and a 592 ball grid array. Its power consumption is moderate (5 watts at 1 GHz and 13 watts at 1.3 GHz), so it can be passively cooled.

	Internally, the Efficeon has 2 ALU units, 2 load/store/add units, 2 execute units, 2 floating-point/MMX/SSE/SSE2 units, one branch prediction unit, one alias unit, and one control unit. This VLIW Processor can execute a 256-VLIW word per cycle, which is called a molecule and therefore has room and capability to execute 8 32-bit commands (called atoms) per cycle.

	The Efficeon has 128k + 64k level 1 cache and a 1Mb or 0.5Mb level 2 cache on the chip. Additionally it has a translation cache for the dynamically translated x86 instructions by the code-morphing software.

	VIABILITY:
	Transmeta lost much credibility and endured significant criticism due to the poor initial Crusoe showing with large discrepancies between projections and actuals for both performance and power. On one hand, the power numbers showed a reasonable improvement over the Intel and AMD offerings. However the end user experience (i.e. battery life) only showed a marginal overall improvement. First, the Code Morphing Software (CMS) combined with cache architecture artificially inflated comparisons between benchmarks and real-world applications. This is due to the repetitive nature of benchmarks and their small footprints. The CMS software overhead may have actually been a key cause of much lower performance for many real-world applications; the simple VLIW core architecture could not compete on computationally-intensive applications; and the southbridge interface was limited by its low bandwidth for graphics or other I/O-intensive applications. Some standard benchmarks even failed to run, questioning its claim of full x86 compatibility.

	The Efficeon addressed many of the Crusoe shortcomings and showed roughly a 2x real-world improvement over Crusoe. In addition, its die size was considerably smaller than either the Pentium 4 or the Pentium M, when compared in the same process technology. Efficeon's die size in 90 nm is 68 mm², which is 60% of the Pentium 4 in 90 nm, at 112 mm², with both processors possessing a 1 MB L2 cache.
	The notion of selling a product into a specific thermal envelope was typically not understood by the mass of reviewers, who tended to compare Efficeon against the gamut of x86 microprocessors, regardless of power consumption or application. One such example of this criticism suggests the performance still significantly lagged Intel's Pentium M (Banias) and AMD's Mobile Athlon XP.


	For the thermal envelope in which Efficeon was designed to compete (7 W and 12 W), there are unsubstantiated claims that its frequency far exceeded anything else in the market, at 1.5 GHz and 7 W, while the Centrino at the time could only operate within the 7 W envelope when its frequency was reduced to 1.1 GHz. This claim also admittedly considers only CPU frequency and does not consider other very significant factors in overall performance, such as core CPI (clocks per instruction), or memory performance and bandwidth, which have varying impact on different benchmarks and system configurations.

	Unfortunately for Transmeta, other components within a laptop computer also consume power, such as the LCD display and Hard disk drive. Since laptops with Transmeta CPUs share these components with regular laptops, the net increase in battery life was not large enough to make much difference to customers.


















	CONCLUSION

	Future Processors
	Transmeta made its name on providing chips for ultraportable devices, but it is looking at expanding its business into thin-client and embedded devices as well.
	Future processors from Transmeta will arrive with twice as much cache, faster buses, and the ability to do significantly more work per clock cycle

	Transmeta prefers to introduce more significant architectural changes on mature process technologies, and plans to introduce the third generation of Efficeon as the technology matures .

	The company is doubtful that the benefits of dual-core technology extend down into the low-power mobile processor world, and asserts they only apply to high-end processors that have run out of any other ways to increase performance.

	Transmeta's presence at Computex is also being used to launch a new push to win customers in China and South Korea.. Transmeta has been successful in Japan, with several notebook PC makers offering products based on its processors.
	The system is being codeveloped by Transmeta and Japan's NEC Electronics Corp. and manages transistor leakage to help reduce power consumption








	REFERENCES

	www.wikipidia.com

	www.transmitta.com

	www.embedded.com

	www.houstuffworks.com

	www.pcworld.com







	Additionally the Efficeon CMS (code morphing software) reserves a small portion of main memory (typically 32 MB) for its translation cache of dynamically translated x86 instructions.

	==Products==		==Products==
	[[image:Sharp PC-MM2 frontal view.jpg\|thumb\|250px\|1 GHz Efficeon TM8600		]
			* ] A532 (was also sold as IRu Stilo 1715L, Fudita Smart TM1000)
	used on Sharp Mebius MURAMASA / PC-MM2]]
			* ] t5710 ]

			* ] ]<ref></ref> (first generation)
	* ] ]
	* ] ]
	* ] ]
	* ] ]
	* ] ]
	* Orion Multisystem ]		* Orion Multisystem ]
			* ] Actius MM20, MP30, MP70G
	* the first generation ] ]<ref></ref>
			* ] Mebius Muramasa PC-MM2, PC-CV50F
	* ] ]

	== References ==		==References==
	{{reflist}}		{{reflist}}

	==External links==		==External links==
	*		*
	*		*
	*		*
			*

	]		]
			]
			]
	]		]
	]		]
	]		]

Latest revision as of 18:44, 7 September 2024

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The Efficeon (stylized as efficēon) processor is Transmeta's second-generation 256-bit VLIW design released in 2004 which employs a software engine Code Morphing Software (CMS) to convert code written for x86 processors to the native instruction set of the chip. Like its predecessor, the Transmeta Crusoe (a 128-bit VLIW architecture), Efficeon stresses computational efficiency, low power consumption, and a low thermal footprint.

Processor

Efficeon most closely mirrors the feature set of Intel Pentium 4 processors, although, like AMD Opteron processors, it supports a fully integrated memory controller, a HyperTransport IO bus, and the NX bit, or no-execute x86 extension to PAE mode. NX bit support is available starting with CMS version 6.0.4.

Efficeon's computational performance relative to mobile CPUs like the Intel Pentium M is thought to be lower, although little appears to be published about the relative performance of these competing processors.

Efficeon came in two package types: a 783- and a 592-contact ball grid array (BGA). Its power consumption is moderate (with some consuming as little as 3 watts at 1 GHz and 7 watts at 1.5 GHz), so it can be passively cooled.

Two generations of this chip were produced. The first generation (TM8600) was manufactured using a TSMC 0.13 micrometre process and produced at speeds up to 1.2 GHz. The second generation (TM8800 and TM8820) was manufactured using a Fujitsu 90 nm process and produced at speeds ranging from 1 GHz to 1.7 GHz.

Internally, the Efficeon has two arithmetic logic units, two load/store/add units, two execute units, two floating-point/MMX/SSE/SSE2 units, one branch prediction unit, one alias unit, and one control unit. The VLIW core can execute a 256-bit VLIW instruction per cycle, which is called a molecule, and has room to store eight 32-bit instructions (called atoms) per cycle.

The Efficeon has a 128 KB L1 instruction cache, a 64 KB L1 data cache and a 1 MB L2 cache. All caches are on die.

Additionally, the Efficeon CMS (code morphing software) reserves a small portion of main memory (typically 32 MB) for its translation cache of dynamically translated x86 instructions.

Products

Elitegroup A532 (was also sold as IRu Stilo 1715L, Fudita Smart TM1000)
Hewlett-Packard t5710 thin client
Microsoft FlexGo Computer (first generation)
Orion Multisystem Cluster Workstation
Sharp Actius MM20, MP30, MP70G
Sharp Mebius Muramasa PC-MM2, PC-CV50F

References

Microsoft brings Vista to developing world PCs

External links

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