Misplaced Pages

Library (electronics): Difference between revisions

Article snapshot taken from Wikipedia with creative commons attribution-sharealike license. Give it a read and then ask your questions in the chat. We can research this topic together.
Browse history interactively← Previous editContent deleted Content addedVisualWikitext
Revision as of 14:00, 21 February 2008 edit210.212.4.234 (talk)No edit summary← Previous edit Latest revision as of 05:01, 21 June 2009 edit undoRadagast83 (talk | contribs)18,709 edits completed merger 
(6 intermediate revisions by 5 users not shown)
Line 1: Line 1:
#REDIRECT ]
{{mergeto|Standard cell|Talk:Standard cell#Proposed_merge_from_Library_.28electronics.29|date=October 2007}}
{{Wikify|date=April 2007}}

In ] design, '''library''' often refers to a collection of cells, macros or functional units that perform common operations and are used to build more complex logic blocks.

A '''standard cell library''' is a collection of low level logic functions such as AND, OR, INVERT, flip-flops, latches and buffers. These cells are realized as fixed height, variable width full custom cells. The key aspect with these libraries is that they are of a fixed height, which enables them to be placed in rows, easing the process of automated digital layout. The cells are typically optimised full custom layouts, which minimise delays and area.

A typical standard cell library contains two main components:
#Timing Abstract (This is generally in the Synopsys Liberty format)<br>This provides functional definitions, timing, power and noise information for each cell.
#Layout Abstract (Common formats that are in use are the Cadence LEF format, and the Synopsys Milkyway format)<br>These contain reduced information about the cell layouts, which is sufficient for automated "Place and Route" tools.

They also may contain the following additional components:
#A full layout of the cells
#Spice models of the cells
#Verilog models or VHDL Vital models
#Parasitic extraction models
#DRC rule decks

An example is a simple XOR logic gate, which can be formed from OR, INVERT and AND gates.
There are many gates available in the electronics library they are simply implemented in the circuit through ICs different ics are available for different logic gates and certain code words are defined for them.
Two logic which can be used to implement any logic gate are NAND and NOR gate.So this logic gates are called UNIVERSAL logic gates.]<!-- I believe this is a relevant example. If someone can verify this, please feel free to remove this comment -->

{{electronics-stub}}

Latest revision as of 05:01, 21 June 2009

Redirect to: