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How to test does a MOSFET work?

I have a damaged video card PCI express for a computer. I've seen various ways for testing but it isn't explained I am suppose to test the MOSFET when there is a power source connected or I can test when it is offline (not powered on). I have a multimetter Metex ME-32. I've calculated that there is less than 1k omh when cheking the gate and drain (around 125 omhs resistance) and 36 mega omhs when cheking source and drain the same resistance is for source and gate. Does this means the MOSFET is damaged? I didn't apploed current and used only the one coming from the multimetter. --LucaTurilli89 (talk) 11:00, 7 January 2010 (UTC)

Splitup in progress

splitup of article Field effect transistor in progress, please see Talk:Field effect transistor Pjacobi 20:45, 19 Jul 2004 (UTC)

• Done Pjacobi 21:19, 19 Jul 2004 (UTC)

The explanation is too difficult for an Misplaced Pages article

Pictures are missing, all presentation is hold in place by formulas. The entire article flow is hard to grasp for a beginner.

Copied from pre-splitup Field-effect transistor

Most of what I've done here doesn't need any explanation, but there's one correction I think warrants a note. I replaced every instance of "glass" with "oxide". This is because the silicon dioxide layer under a gate is not glass. Glass would not work. A glass is an amorphous solid - irregular arrangement of atoms. The common usage of "glass" happens to be an instance of this. SiO₂ in MOSFETs is crystalline, not glass. -- Tim Starling

Small correction: amorphous oxides can work perfectly well as gate oxides. see link. At least as far as I know, these films are almost entirely amorphous. The best films are done with ECR, but you can also use PECVD and get decent results. On physical grounds, I don't see any reason why a gate dielectric has to be crystalline in "work". --User:Dgrant

In fact, crystallinity is an undesirable effect in gate dielectrics, as it creates grain boundaries, which can dramatically increase gate leakage. User: Stonecold21

You're the man Dave, I'll take your word for it. Before you came along, I didn't know amorphous oxides were used for anything other than window glass :) I notice that the resistivity of the oxide in your reference is many orders of magnitude less than for crystalline silicon. That would degrade performance somewhat, but at least the breakdown voltage is still high. -- Tim Starling

"Oxide" is more correct than "Glass". A glass is not only amorphous but it also contains lots of impurities of highly mobile ions as softener, making it very inadequate as gate oxide. Dgrat is right about amourphous oxides, although they will result in very instable transistors. In organic transistors, even polymers are used as gate dieletric. --Qdr 17:12, 17 Jul 2004 (UTC)

what does "whereas those to the left abstract from the body contact." mean? It doesn't make any sense to me, or at least is doesn't convey the indended meaning, in my mind. dave

It doesn't mean anything. I changed it to something which makes sense, and is probably right. I seem to remember seeing some FET-like structures with the body insulated from the backside, but I don't think they do that for MOSFETs. -- Tim Starling 00:39 May 14, 2003 (UTC)

You have that in SOI (Silicon on Insulator) FETs, but these work slightly different.--Qdr 17:12, 17 Jul 2004 (UTC)

mosfet symbols

The schematic for your MOSFET shows a solid line connecting the Source and Drain. Does this not indicate a depletion mode MOSFET?. An enhancement mode MOSFET is symbolically shown with a dashed line between the Source and Drain.

The arrows for the 'metallurgical' contacts point at the bottom of the N diffusions. The metal contact is on the top surface. Shouldn't your arrows point to the upper surface of the N regions?.

All textbooks use different notations. I can't remember right now what is right, and what is depletion, enhancement, etc... However, should use standard IEEE conventional symbols, whatever those are, and we should state that they are the IEEE standard symbols. If there are some common "misuses" of the symbols out there, then we should mention that. So first thing I think is to check IEEE and see if there are standard symbols, and secondly to check something like Art of Electronics and see what it uses. dave 22:06, 16 Oct 2003 (UTC)

IEEE: http://ewh.ieee.org/soc/es/Nov1998/14/education/

You are right about the 'metallurgical' junctions, they are on top of the diffusion region and are not the same! Modern FETs do not only use high doping, but also metal silicides at this place.--Qdr 17:12, 17 Jul 2004 (UTC)

MOSFET section

I'm planning on doing a lot of work on the MOSFET section. I hope to discuss how MOSFETs are evolving to smaller and smaller submicron dimensions, and the problems designers are encountering...obviously non-technically. I've created two subcategories I want to expand upon--why MOSFETs are so popular and the problems with scaling. Rmalloy 13:47, 14 Jul 2004 (UTC)

I think some work needs to be done in the introduction to MOSFET...most important part. for later. Rmalloy 18:38, 14 Jul 2004 (UTC)

Thanks for your efforts! I assume at some point it would make sense to put all MOSFET stuff in separate article. Agreement? Pjacobi 19:26, 14 Jul 2004 (UTC)

I dunno, I'm new here and don't know what the protocols are. As long as info is easily accessible it makes little difference to me. I'm not going to touch stuff like that. Rmalloy 20:06, 14 Jul 2004 (UTC)

It could make sense to have a rather generic introduction to FETS on this page and move all the details (different types, processing, materials) to other pages. --Qdr 17:12, 17 Jul 2004 (UTC)

• • • • Splitup plan, please comment under each point if necessary. If no active disagreement is seen, I'll do the splitup around 2004-07-19 21:00 UTC. Pjacobi 18:49, 18 Jul 2004 (UTC)
        • The MOSFET specific parts of Field Effect Transistor will be moved.
        • This applies to section MOSFET (currently 1.1) and DMOS (currently 1.5).
        • It will go to http://en.wikipedia.org/w/wiki.phtml?title=MOSFET&redirect=no which is currently a redirect.
        • The JFET, MESFET, and HEMT sections are not yet substantial enough to be moved to separate articles.

Sounds good, but I think also the other types of FET devices should be moved somewhere as they are way too specialized for a generic introduction. Maybe an article about "special" or "exotic" FETs? --Qdr 19:59, 18 Jul 2004 (UTC)

Lumping together JFETs and MESFETSs into Field effect transistor (exotic) (or ?) will break my heart ;-). I'd vote keeping them (temporarily) in the main article, or as a second choice, make all separate articles, even when HEMT will be a short one. Pjacobi 21:34, 18 Jul 2004 (UTC)

I vote for separate articles, maybe that is also an incentive to extend the individual articles a little. And btw, there should also be a link to TFTs in the main FET article. --Qdr 22:17, 18 Jul 2004 (UTC)

I second this. With some diagrams all of these transistor types would be good separate articles. I think Field effect transistor should be a list of links. Maybe some generic discussion. Rmalloy 00:14, 19 Jul 2004 (UTC)

Rmalloy: There are some inaccuracies in your additions: The reason for using polysilicon as a gate material is the reduction of interface states and the self aligned S/D diffusion. Replacing it with metals (for example TaN, TiN) is subject of current research. Current gate oxide thicknesses are way below the 20nm you stated, I changed it to 2nm. But somebody should look up an accurate number. The problem with thin oxides is not breakdown, but leakage by quantum mechanical tunneling of electrons through the oxide. To remedy this, the industrie works on high-k dielectrics.--Qdr 17:41, 17 Jul 2004 (UTC)

QDR: First-off, I must admit that I haven't worked in this area for 2 years. But I think I am right about the polysilicon gate. The self-aligned S/D diffusion process would work equally well with a metal gate. I went back and looked at some stuff I wrote on www.everything2.com when I was a grad student in this area. Look at the article MOSFET that describes and shows diagrams of the fabrication process. The self-alignment process work the same if the gate were aluminum. I'm 99% sure that the reason you can't use aluminum is that there is a high-temperature annealing step after the gate is deposited, and this would melt aluminum. Now the reason the annealing must be done after the gate is deposited relates to the self-alignment process (S/D to be annealed created after gate), so we could be both right in a sense.

I looked up the melting points of the metals you mention, and they have very high melting points. When I was a grad student, I don't recall much effort into using these metals as gates. I don't know why, so I won't argue. But I do remember heavy emphasis on the silicides, like I wrote in this article. I know what surface states are, but I don't see how they relate.

2nm is the accurate number. I meant 20 angstroms. 2nm was considered an absolute cutoff.

Now my memory is that 2nm is still a long way for an electron to tunnel. I seem to recall that, like I said, the oxide broke down, creating states in the oxide that acted like rocks across a river that you can jump across, facilitating tunneling. So I won't argue with you here...we might both be right. And it's not worth arguing. But I'm 99% sure that 2nm was the cutoff, considered absolute by the chief technology officer of TSMC. And I agree about the high-K dielectrics, and mentioned it in the article. Rmalloy 18:54, 17 Jul 2004 (UTC)

I did some quick websearching. An Intel site claims successful operation with 1.2nm of gate oxide, so I guess I'll have to bite my tongue on 2nm. And I'm reminded of another key issue for gate materials--work function. The current setup, where the source, drain, and gate are all doped heavily at the same time gives the gates the proper work function for the transistor type--NMOS or PMOS. Successful metal gate processes would require two kinds of metals--one work function for each transistor-type. It's dawning on me that the choice of gate materials involves several issues, including all the ones we've mentioned and probably several more.

Feel free to clean up, correct, or add to anything I wrote. These issues are complex and there are many issues to discuss...maybe it would be best to avoid difficult issues like this altogether in an encyclopedia. Phew I'm glad I left this field! Rmalloy 16:35, 18 Jul 2004 (UTC)

The oxide thickness is a moving target, IMO around 2nm is a good guess. Intels 1.2 nm oxide was probably already nitrited oxide. There are many candidates for new metal gates, however the ones I quoted have been announced by the IMEC recently. And yes, there are various leakage mechanisms (poole frenkel, schottky emission into insulator valence band, direct tunneling, fowler-Nordheim) and they are enhanced by soft breakdown, however they are usually not regarded as breakdown itself.

I am pretty sure that the main incentive to use polysilicon gates was the self aligning SD process, back in the 70ies. I do not know the exact problem with Al gates and the self aligning process, but for example the spacer oxide would be pretty difficult to apply to an Al-Gate. Anyways, all of this is way too detailed for a Misplaced Pages article, the best way is to formulate it as generic as possible. --Qdr 19:59, 18 Jul 2004 (UTC)

Good point about the spacer. I have the melting thing stuck in my head...I must have picked it up somewhere. I agree this is all too detailed for Misplaced Pages, but I guess I thought some explanation for the polysilicon gate would be advisable. At first glance, polysilicon is a very strange choice for gate material. You obviously know what you're talking about, so don't hesitate to delete or change anything I wrote. Rmalloy 00:14, 19 Jul 2004 (UTC)

Analog circuits

I've added all I feel comfortable adding about MOSFETs in analog circuits. I wish someone could discuss analog stuff, since everything is so digital digital digital. Rmalloy 23:38, 14 Jul 2004 (UTC)

Try contacting one of the engineers at National Semiconductor (www.national.com). I don't work for them, but their stuff is good. User:rank newbie 184.76.184.200 (talk) 02:11, 12 March 2011 (UTC) A quesiton: "The MOSFET's strengths as the workhorse transistor in most digital circuits does not translate into supremacy in analog circuits, in which the bipolar junction transistor (BJT) has traditionally been seen as the transistor of choice, due largely to its high gain." This does not seem correct, since FETs have near-infinite gain - essentially no current flows into the gate. Glengarry 21:09, 15 Jul 2004 (UTC)

Bad subject-verb agreement for one thing :(.

Ok, this is not an area I know a lot about, but let me try to explain as best I can. "Gain" invariably means "small signal voltage gain" (output signal voltage / input signal voltage). The fact that a MOSFET gate allows no DC current isn't relevant (though its true). The job of analog circuits is to handle small signals.

Suppose a transistor is being used for amplification in an analog circuit, it is "DC biased" to put it in the high gain regime. A small signal voltage is applied between gate and source (or between base and emitter), creating a small signal current from drain to source (or from collector to emitter). The ratio of this small signal current to the small signal voltage is called "transconductance." My sense is that BJTs have substantially higher transconductance than MOSFETs. For a tiny bit of support, see http://www-inst.eecs.berkeley.edu/~ee130/SP03/homework/hw13soln.pdf. This small signal current may drive a resistive load, giving an small signal output voltage of the current times the resistance of the load. Thus you end up with a higher "gain" (output voltage/input voltage).

I'm really shaky on everything analog, and that's why I made such a vague statement. I just felt like it would be inappropriate to only talk about digital stuff when analog circuits are very important. I think what I wrote is essentially correct, but if someone wants to delete it that's fine. I'd rather someone teach me though! Rmalloy 00:42, 16 Jul 2004 (UTC)

The gain issue is easily misinterpreted and is always good to start a flame war at news://sci.electronics.* or http://www.diyaudio.com. I'd write something into article but for the fear of a edit war! In essence there are four quantities which can be seen as geen dV(out)/dV(in), dI(out)/dV(in), dV(out)/dI(in), and dI(out)/dI(in). Of course MOSFET score big on dV(out)/dI(in) and dI(out)/dI(in) in NF, as no input current flows, but the practical significance is more that there is moe leeway in designing the preceeding stage.

What's more the problem with MOSFETs in discrete designs, is the variabiliy of there threshold voltage.

Pjacobi 07:27, 16 Jul 2004 (UTC)

It's not true that no *small signal* input current flows into a MOSFET. Current is constantly charging and discharging the MOSFET gate, so dI(in) != 0. In fact, capacitors, like the MOS capacitor, are short-circuits to high-frequency current. I think this topic is probably best left alone in the article unless someone is an expert on the subject, so we avoid misinformation.Rmalloy 13:04, 16 Jul 2004 (UTC)

Agreed that the transconductance of a BJT is favorable compared to a MOSFET. I'll made the change in the article. Thanks, Glengarry 14:56, 16 Jul 2004 (UTC)

I edited the analog section of this article to add a few things. I took out this section from it because I thought it sounded kinda weird and it isn't exactly true:

"Some analog circuits are designed solely using MOSFETs in a fabrication process specialized for digital circuits because it is advantageous to incorporate digital and analog circuits onto the same chip and digital fabrication processes are less expensive."

Any difference between the analog and digital fabrication process would have to be changed to incorporate the analog components. I am also not aware of any difference, although that doesn't mean there isn't one.

Big mistake

This statement is not correct: "The MOSFET includes a channel of n-type or p-type semiconductor material (see article on semiconductor devices), and is accordingly called an NMOSFET or a PMOSFET (also commonly nMOS, pMOS)." Actually an NMOS normally has a P-type channel material. The conductivity of NMOS or PMOS is dominated by electron current and hole current respectively, which is the root for theri definition.

Deleted Section

The channel in a MOSFET is connected on each end to source and drain terminals which are oppositely doped in relation to the channel, and highly doped so that they form low-resistance "ohmic contacts" with metal wires. It is well-known among electrical engineers that a p-n junction allows current to flow only in one direction, from p-type semiconductor to n-type. Since the structure of the MOSFET consists of back-to-back, but oppositely directed, p-n junctions, the MOSFET allows no current to pass in the "off" state, in which no voltage is applied to the gate.

Comment

I've overlooked this when doint the split up. The first sentence is somewhat O.K. But there a no pn-junction in the MOSFET conduction path. It's: ohmic contact - n+ - n-channel - n+ - ohmic contact. Some hard work to do here, perhaps a new picture is needed, adding the n-channel zone under the gate. Pjacobi 21:31, 23 Aug 2004 (UTC)

The picture is perfect. It illustrates the MOSFET's *construction* and was never meant to show the various depletion, inversion and accumulation layers that form, widen, compress and vanish during its *operation*. It would take four pictures just to explain the MOSFETs most important operating conditions (thermal equilibrium, cut-off, strong inversion, saturation), and more such conditions exist. It is my current belief that Misplaced Pages entries should be edited in the style of a vivid and concise encyclopedia, but not as exhaustively as if for a comprehensive engineering or physics textbook.

Also, two pn-junctions definitely exist. It is precisely the reverse-biased drain junction that prevents current flow in cut-off condition, for instance. The "ohmic contact - n+ - n-channel - n+ - ohmic contact" conduction path suggested above exists in strong inversion exclusively and gets disrupted in saturation although current continues to flow! Kaeslin 17 Sept 2004.

Sorry, if I got this wrong, feel free to revert. But isn't the MOSFET typically depicted as a unipolar device, especially in popular presentations, stresseing the difference to the BJT? So that the picture, even when perfectly illustrating the construction may give a false idea of operation to the non-technical reader? Pjacobi 09:47, 17 Sep 2004 (UTC)

Yes, the label "unipolar" is sometimes being used since the charge carriers are electrons or holes exclusively (in n- and p-channel devices respectively) as opposed to BJTs where both types of carriers are involved in the same transistor. I might indeed reinclude the figure if I find leisure to do so. Kaeslin 16:00, 20 Sep 2004 (UTC).

One thing that is definitly wrong is the remark about the "metallurgical junctions". If they are to be mentioned, they should be properly marked on top of the diffusion regions.--Qdr 16:28, 17 Sep 2004 (UTC)

No, the term "metallurgical junction" refers to the borderline between n- and p-doped semiconductor regions. What you want between the diffusion regions and the metal plugs that connect to them are ohmic contacs, not junctions. Kaeslin 16:30, 20 Sep 2004 (UTC).

Resistance Calculations....

The wiki says, "Conceptually, MOSFETs are like resistors in the on-state, and shorter resistors have less resistance." From the basic ${\displaystyle R=(pL)/A}$ surely reducing the length would not change the resistance?

EG: for this example lets make rho=5; let the width of the channel=2 and we will vary the length. If we start with the length at 10, the resistance will be: ${\displaystyle (5*10)/(10*2)=2.5}$ If we reduce the length to 5, the resistance will be: ${\displaystyle (5*5)/(5*2)=2.5}$

(NB: this is my first wiki edit and I've probably broken loads of conventions. Could someone please edit/delete this, whatever is appropriate)

The A in your formula is the area formed by the other two directions, so to speak width and height of the channel, not length.

But the article chapter you are referring to is nevertheless a but fishy .

Your edit was just fine, you only missed to use the "auto signing" feature of the software, putting four tildes at the end of your discussion statement, would give user and date/time info.

Pjacobi 22:50, 5 Dec 2004 (UTC)

Graphical Representation of MOSFET operation in circuits

Would it not be usefull to include Vin/Vout graphs? i.e. what the 'resistance' across the MOSFET does as the gain-source voltage increases? Yossarian 10:19, 11 Jun 2005 (UTC)

Need some help on MOSFET and Square wave high amp inverting

Guys and gals, can you help me a little bit. I have this idea of buildng a square wave AC source from a constant current 300A DC. I can, hopefully, use an H bridge and MOSFETs. My question is, if I use (stepped down) AC to control the gate of the MOSFET, the resulting voltage would not be square wave, or would it be? Any thoughts? thanks. I will be watching this page.

BJTs better for some digital circuits?

At the end of "The Primacy of MOSFETs", the article currently states, "Ironically, the BJT has some advantages over the MOSFET in certain digital circuits; digital circuit designs can incorporate BJTs to speed signals in critical locations." Could somebody clarify this? Exactly what advantages do BJTs have in what sort of digital circuits? Does the wording here indicate that BJTs are faster than MOSFETs for digital switching? (if so, shouldn't this actually be mentioned explicitly?) -- Foogod 12:16, 28 November 2005 (UTC)

• My guess is that the author didn't know what bipolar circuit it was exactly. The author was probably referring to emitter coupled logic Dunno if an article exists for it Snafflekid 19:12, 28 November 2005 (UTC)

The way you define digital circuits is where the nuance comes in. In many chip-to-chip digital communication protocals BJTs are used, but they operate on low-swing voltage signals. Is that digital, well, because they are working on '1's and '0's it can be considered digital, but because the representation of a '1' and '0' is in an unconventional low-swing voltage it's really an analog signal. So it's really a tossup. These serial communication links have gone up to 40GB/s, and then are parallelized in the digital chip with demultiplexors, and are used in the chip. Both the demultiplexors and the rest of the chip use MOSFETs. -- Jeff3000 19:58, 28 November 2005 (UTC)

Sounds like TTL. - mako 06:44, 29 November 2005 (UTC)

BJT's are currently better for at least 3 jobs: The first is in high speed switching because they don't have the "larger" capacitance from the gate, which times the resistance of the channel gives the intrinsic time constant of the process. Widening the channel reduces the resistance of the channel, but increases the capacitance by the exact same amount. Reducing the width of the channel increases the resistance, but reduces the capacitance by the same amount. R*C=k, 0.5R*2C=k, 2R*0.5C=k. You can skip most of this problem with a BJT. The second job stems from the first: When driving many other gates the resistance of the MOSFET is in series with the gate capacitance's of the other FETs, creating another time constant. This is how delay circuits work. BJT's are better to drive the other gates because they output much more current per unit area, which causes the gates to charge faster and decreases the time constant, increasing the speed. The third job is high current amplification, such as in audio and motor control applications. MOSFET arrays where possibly thousands of MOSFETs are placed in parallel( I haven't seen any chips with millions in parallel) to provide the current, although these circuits suffer from the timing issues discussed above and usually use at least 1 BJT to drive the MOSFET array.--Jeffrobins 17:28, 2 May 2006 (UTC)

I'm 99% certain that the conclusion in Depletion mode MOSFETs section is the opposite of the information given in the beginning

You're right. I've corrected it. -- Jeff3000

Need for tidying?

Hi,

I plan to contribute to both the "power MOSFET" and "MOSFET operation" sections. The problem is that the article is relatively long now, and adding content to these sections will increase the "bloated" aspect of the article.

Furhtermore, there is a mix between power qnd microelectronics MOSFET in some section which make the whole not exactly consistent (for example, the termal runaway of power MOSFET is addressed in the "scaling" section, which is specific to microelectronic MOSFETs).

I think it is time to split the article, with a main root about the generic principle of a MOSFET and its history, and then articles about integration, power, maybe manufacturing. What do you think? CyrilB 12:18, 2 April 2006 (UTC)

Well, I'll will say that nobody is against some transformations on the article. I will start by creating a different article MOSFET model to put all the equations (and demonstrate them by the way), as they add little to the understanding of the principle and might frighten people... I think the MOSFET scaling should also go in its own article, but I'm not really an expert about this issue. -- CyrilB 18:50, 6 April 2006 (UTC)

I didn't notice your first comment because the comment edit had to do with bjt operation in digital circuits. I think you're on the right step to divide up this article, but I don't think moving out the equations is the right step. There's not much that can be added to that, so that article would remain small. We have to move out a section that has room for growth. So I would suggest moving out the Power Mosfet (as it's quite different) out into it's own artcile with a summary section in this page. That would shorten the article considerably. -- Jeff3000 19:09, 6 April 2006 (UTC)

I take back my comment a little, the Power MOSFET section by itself is not big enough, so I would move all the other MOSFET types out and use just the microelectronics MOSFET on this page. We would put a disambiguation link at the top of the page, with a short section in the bottom of the page, that other types of MOSFETs also exist. -- Jeff3000 19:13, 6 April 2006 (UTC)

Actually, the equation part and the power MOSFET section are the two parts on which I plan to work, so they should grow in the near future. And both the microelectronics MOSFET and the power MOSFET share the same principle. So I think the MOSFET article should be more focussed on the history and basic principle of the MOSFET, and link to specific types. -- CyrilB 19:50, 6 April 2006 (UTC)

How bout you first work on moving out the Power Mosfet stuff, and if need be (through your additions in the equations) we'll move out the equations. In my mind the equations need to be on this page. -- Jeff3000 20:39, 6 April 2006 (UTC)

Done. But the page is still very long. Anyway, lets see how things go. -- CyrilB 21:34, 6 April 2006 (UTC)

Terminology Error

Hey, this article has a terminology error in it. I tried to correct it but it was changed back without thought and I don't want to get into an argument.

Digital MOSFET circuits operate in the cut-off and linear region, while the saturation region is used mostly for analog amplifiers. Just think about it from the IV curve: when the Vds is small we are in the linear region. If using the the FET as a switch in the saturation mode you'd have a larger Vds, not good for a switch. I noticed the same problem on the switching amplifer site and corrected it, although that's probably been changed back by now too.

Am I missing something here? Did they decide to clean up the terminology and not tell me?

Sorry about all the edits, I am a newbie here (but not to engineering!). -- Dkomisar

No, you're right. It's been re-corrected. - mako 21:29, 2 May 2006 (UTC)

Modes of Operation

I deleted this statement:

In digital circuits MOSFETs are operated in cut-off and linear mode. The saturation mode is mainly used in analog circuit applications.

Its true that in steady state, the mosfets in a digital circuit are either in cut-off or linear mode. But any time a cmos stage is switching, there is a transistor in saturation mode. Rather than complicating the statement to make it accurate, I just removed it; I thought it seems like an extraneous point. —Kymacpherson 04:42, 13 June 2006 (UTC)

Thanks for fixing that. I was just reading the previous talk where it went back and forth. Some of us are old enough to remember metal-gate pMOS with saturated loads, and silicon-gate nMOS with sometimes-saturated depletion loads, too. But as you say, in CMOS the interesting parts, namely the switching events, are done by transistors in saturation. Dicklyon 05:18, 30 August 2006 (UTC)

Editted image

I made an update of that image to make it more clear. If anyone likes it, please install it. The new name is simply MOSFETs.jpg. Dicklyon 04:40, 30 August 2006 (UTC)

Nobody home here, so I'll go ahead. Revert if you disagree. Dicklyon 16:53, 1 September 2006 (UTC)

Does anyone happen to know if the pair of FETs pictured form a functional device? It looks like they could work as a digital inverter, but I can't identify the doping regions just from looking at the photo... -- mattb @ 2006-09-11T04:10Z

That layout is not compatible with the idea that one is an nFET and other a pFET, since they share a source/drain contact of one type. Nonetheless, you could bias one device to act as a saturated load, by setting its gate near threshold, and use the other gate as input, and make a functional inverter that way. But, no, it's not designed to be an inverter, I would say by looking at it. I don't know where the picture came from. Dicklyon 04:15, 11 September 2006 (UTC)

It is possible to make an inverter using strictly nMOS or pMOS. Based on the dimensions of the two devices, I would say that the two FETs would most definately function as a basic inverter if properly biased.

It should be noted that added label on the photo "are added afterwards". It is my opinion. What others think?
Čikić Dragan (talk) 20:27, 15 December 2008 (UTC)

The labels were added after the image was enhanced. Are you suggesting that we need to say that in the caption? Or that we should leave the labels off, so that they can be added in other languages? Or what? Dicklyon (talk) 04:51, 16 December 2008 (UTC)

SVG symbols

Omegatron, good job on the SVG schematic symbols. I was considering doing something myself, but I'm a novice at SVG editing and not very comfortable with Inkscape yet (you know anything better on Mac OS X?). Just a couple of things I recommend changing:

• P-channel JFET: the gate arrow should come out of the source side, like the N-channel, not the drain side; just swap the labels S and D. Alternatively, JFETs are usually drawn with the arrow centered, but then there's no defined choice of S and D.
• The simplified MOSFET symbols are usually drawn with the bar extended to the same length as the triple bar in the complex symbol. For example, more like this one:

I'll work on it if you prefer. Dicklyon 01:54, 10 September 2006 (UTC)

I didn't create them, except for the simplified ones. See Commons:User_talk:Jjbeard#FET_symbols. The simplified ones can be drawn either way: I was just copying the bitmap diagram that was in the article previously. — Omegatron 02:55, 10 September 2006 (UTC)

Yeah, I didn't like it before, either. They CAN be drawn either way, but the lazy way is ugly, and less like the official way. I'll work on them at some point if you don't want to. Dicklyon 03:16, 10 September 2006 (UTC)

One more thing: a more complex issue. The complex MOSFET symbols, both depletion- and enhancement-mode, show the bulk or body terminal connected to the source. This is typical in single packaged transistors, but by no means the only widely used configuration. In typical ICs, most of the transistors have their bulk, body, or "back-gate" terminal connected to a power supply (VSS or VDD) rather than to the source; about half the time it's the same node, and of the ones with source not at VSS or VDD, the bulk is usually, probably 99% of the time, not connected to the source. So, ideally they are drawn as four-terminal devices, since that's how they are always used in IC designs. Dicklyon 02:46, 10 September 2006 (UTC)

I know. I was going to draw every permutation of transistor symbol, in the same style, size, and line width and everything, but I really don't have time. I saw these were already drawn and decided to go with them for now. I agree that both types of symbols should be shown. — Omegatron 02:55, 10 September 2006 (UTC)

Thermal runaway

You're both wrong. Or both right. A quick GBS search shows verifiable sources for both positions (that thermal runaway is "impossible" or "widely known"). So we need to represent both in the article, instead of a revert war. Here's one that says "less prone to" Dicklyon 00:55, 9 October 2006 (UTC)

I got this on my user page from an unregistered user, and answered it, but nobody is likely to see it there so I'm copying it here:

A few days I corrected your info on the MOSFET page, relating to thermal runaway. You then changed back that section, saying in comment that it didn't make physical sense. So let me try to explain it to you... Assume that a MOSFET device turned ON works as a resistance (which is true for DC current). Now imagine a circuit that connects a N-channel MOSFET's source to the negative of a 9V power supply and it's drain to the positive of the same supply. Assume also that the gate is biased so as to turn the MOSFET fully ON and that it's ON resistance is 1 ohm. The current following in this circuit will be 9V / 1 ohm = 9 Amps. Now let the MOSFET heat up and increase it's resistance to 3 ohm (typical increase at 125º C). The current flowing will now be 9V / 3 Ohm = 3 Amps. Now for the punchline : the power dissipated on a resistance is 'Power dissipated = Resistance x Current squared'. So for a cold MOSFET you'd get a dissipation of 1 Ohm x 9 Amps x 9 Amps = 81 Watts. And for a hot one 3 Ohm x 3 Amp x 3 Amps = 27 Watts. This means that thermal runaway is impossible. If you want to you can use the more known formula 'Power = Voltage x Current'. So with MOSFET cold Power = 9V x 9 Amps = 81 Watts, with MOSFET hot Power = 9V x 3 Amps = 27 Watts. Your info would only be correct if the current flowing through the MOSFET was constant. But then the voltage applied to source-drain would have to increase, which normally doesn't happen. Hope this clears up your misconception, and if you would be so kind as to correct the page... ;-)

Carlos Azevedo

Carlos, yes, that analysis is correct for a MOSFET switch connected across a power supply. However, a more typical situation is to have the MOSFET driving a load, with a load resistance that's higher than the MOSFET's on resistance, usually by a large margin, so that the load is receiving more power than the MOSFET is dissipating during the on state. In this case, increasing the on resistance makes the power dissipated in the MOSFET go up, not down. That's why thermal runaway is still possible. It is closer to the constant-current case, and the drain voltages does increase in this typical configuration. Please do a couple of calculations for such a configuration, and let me know if you accept this analysis or not. It's probably still a good idea to revise the article to state approximate conditions under which thermal runaway is possible or not, with some references. Dicklyon 17:15, 13 October 2006 (UTC)

Body Effect

I removed this section because it seems out of place. Sure, it's included in Level 1 SPICE, but it's not required for a basic explanation of MOSFET operation. I'd like to see such material on a MOSFET modeling page. - mako 22:14, 24 October 2006 (UTC)

I agree that it could be removed from this page, but it deserves much more that MOSFET modelling. There is a real physical effect when the body is reverse or forward biased. Regards, -- Jeff3000 22:18, 24 October 2006 (UTC)

I disagree that it can be removed. A MOSFET is inherently a four-terminal device, and a qualitative understanding of it in any other than ground-source configuration depends on being aware of body effect. Dicklyon 22:26, 24 October 2006 (UTC)

As the person who added it back, I'm with Dick on this one. Just as he said, MOSFETs are four terminal devices. The body effect is only neglected for the purposes of circuit modeling if the body is shorted to the source or if the designer is doing a quick 'n dirty approximation. As I said in my edit comment, you need only look at any small or large signal model for the MOSFET and you'll find factors accounting for the body effect. -- mattb @ 2006-10-24T22:47Z

Very well, I concede. Things should be made as simple as possible, but not simpler, eh? - mako 23:51, 24 October 2006 (UTC)

Primacy of MOSFETs excessively big-worded

I think the primacy of MOSFETs section could be reworded, since it uses a wide vocabulary that isnt necessarily useful. It sounds somewhat like an advertisement does (although I dont think it was added as advertising, it just reads like one. Examples: "primacy", "possess such technical attractions", "serendipitously", "Buoyed by this stroke of good fortune" and, "electronic hegemony". Kaldosh 10:51, 26 October 2006 (UTC)

What does it do?

OK, the MOSFET, transistors and stuff, I get it.

But what does it do? What do you get out of it that you might want? What do you need to put into it?

I'd suggest reading transistor. A full discussion of "what a MOSFET does" is rather out of the scope of this article and more suited for a semiconductor physics course. In a nutshell, a MOSFET is a type of transistor that uses electric fields at an oxide-semiconductor interface to control the conductivity between two terminals. What you "get out of it" depends on how you use it. Transistors in general can be used for switching, amplification, buffering and impedence matching (followers), etc. -- mattb @ 2006-11-27T16:14Z

Or think of it by analogy with a neuron; the brain is made of billions of neurons, but what do they do? What do you put into them and what do you get out of them? Answer: all kinds of signals, depending on what role they are playing. In one simple configuration, you put in a voltage signal and get out a current signal; in another, you put in a voltage signal and get out an amplified voltage signal. I agree with Matt: start with the transistor article. Dicklyon 16:26, 27 November 2006 (UTC)

Here's a radio schematic in which each transistor is labeled by what it does functionally, in terms of RF (radio-frequency), IF (intermediate-frequency), and AF (audio-frequency) signals. Dicklyon 16:31, 27 November 2006 (UTC)

Though it should be noted that the transistors in that receiver are BJTs rather than MOSFETs. The small signal operation of BJTs and MOSFETs are modeled much the same, but the actual operation and utility of each is significantly different from the other (e.g. BJTs exhibit much higher transconductance and are thus better small signal amplifiers while MOSFETs have very high gate input impedance and are good for buffers, etc). As Dick pointed out, it's impossible to summarize the uses of any transistor in one neat statement. One quick generalization I can make is that FETs (MOSFETs primarily, perhaps HFET/HEMTs) tend to be better switches (digital circuitry) and bipolar transistors (BJTs, HBTs, etc) tend to be better amplifiers (analog circuitry), though they can both be used in either capacity. -- mattb @ 2006-11-27T19:17Z

That's a conventional generalization, but it's less true with modern FETs than it was in the old days. FETs can easily deliver any transconductance value you need, any drive level, any speed, etc. Dicklyon 19:21, 27 November 2006 (UTC)

Sure, but a bipolar transistor of similar physical dimensions will still deliver higher transconductance; just as a good heterojunction system can produce a bipolar transistor with extremely high common-emitter input impedance. BiCMOS exists for the very purpose of leveraging the advantages of both types of transistor. I still think that the generalization is valid. -- mattb @ 2006-11-27T21:09Z

I remain unconvinced. For both types, transconductance is approximately proportional to the output current DC level, with a small numerical advantage to the bipolars. The FETs, however, can often carry more current in a given area, at least in modern CMOS IC and power device technologies. My impression is that BiCMOS is no longer much used; it offers extra circuit flexibility, but there's not much net advantage. Dicklyon 22:48, 27 November 2006 (UTC)

We could go on like this for awhile, but I'd rather not seeing how it's non-critical to this article and the original question. I think we'll just have to agree to disagree for the time being.

Do consider, however, that bipolar transistors I-V relationships are based on exponential law while MOSFETs are (more or less) modeled with a square law. That is part of the reason that BJTs usually have a transconductance advantage. I'm also a bit skeptical about your current claims since you can compensate for current crowding pretty easily in the BJT if high current power electronics are your aim (I've helped design HBTs for high current applications). In general it's the bipolar transistor design that can drive more current because it is limited more by lower extrinsic series resistance than the pinch-off regime that exists in the MOSFET channel.

The IGBT comes to mind, which combines the voltage control and fast switching transient characteristics of a MOSFET with a BJT. This is specifically for high voltage/high current applications where it would be more difficult to create a MOSFET that could handle the required power. On a similar note, last I talked to my contacts at a RF power amplifier company, they use GaP/InGaP HBTs for their high power radio amps. Notice some of Skyworks' high current PAs; they use HBTs. You can be sure they'd be using cheaper transistors (like Si MOSFETs) if they could easily be fabricated to deliver the same kind of gain and power.

Anyway, as I said, I don't really want to continue this discussion since it's not very important to this article at this time. I just wanted to point out that in my humble experience, bipolar designs are inherently superior over MOSFETs for amplification and current driving. Take that for whatever it's worth to you. :) -- mattb @ 2006-11-28T00:26Z

Matt, I do appreciate your experience in this. I just like to be contrarian sometimes. Since a good chuck of my FET experience is in using them in the subthreshold (weak-inversion) region, where their transconductance per output current is almost as high as bipolars, and since that transconductance degrades only gradually as you go above threshold into the quadratic region, I allowed for a "small numerical factor" of BJT superiority there. And I certainly agree that you can get big advantages from exotic (non-Silicon) semiconductors, which are generally easier to make BJTs with than FETs. Anyway, no problem living with our differences. Thanks. Dicklyon 00:33, 28 November 2006 (UTC)

Thanks everyone, that's clear. I had looked it up being told that it was making HVDC transmission more viable, and somehow got the impression that it was a more complex device rather than just a kind of transistor.

Threshold symbol?

I changed the threshold voltage subscript in the triode/saturation/cutoff region because it was labeled incorrectly. For an n-channel MOSTFET, the threshold voltage is written as V_TN, not V_th.

Here are 76 books that disagree with you. Dicklyon 06:48, 30 November 2006 (UTC)

I've seen it written both ways and don't particularly care which convention is used as long as its consistant. -- mattb @ 2006-11-30T15:39Z

In book search, I find TH about twice as common as TN (is that because it's used for both types, as opposed to TN which is for n-type only?). Capitalization varies a lot. Dicklyon 15:46, 30 November 2006 (UTC)

In a couple of my books, they use Vto, as in SPICE (VTO parameter), for all MOS/JFETs. 212.183.240.71 (talk) 15:39, 4 September 2009 (UTC)

Orphaned Derivative Page

The Metal-Oxide-Semiconductor_structure article is an orphaned derivative of this page. Someone needs to either merge any new content there back into this page, or add more unique content to that page and link it from here. Lord Nightmare 22:40, 4 January 2007 (UTC)

I favor the latter. There's an awful lot that can be said about the MOS structure that's independent of whether you make transistors out of them, so that's a good place for it. Dicklyon 00:00, 5 January 2007 (UTC)

I agree with Dick... Anyone who wants to bring the MOS article up to speed is welcome to do so... -- mattb @ 2007-01-05T03:48Z

I also agree... I intended to add more content to this article, and never did. Sorry CyrilB 12:23, 5 January 2007 (UTC)

Metal Gates and recent Intel/IBM announcements?

How are traditional metal gate MOSFETs distinguished from the recently announced Metal Gate CMOS processes? These announcements proclaim that FETs have been built using polysilicon for 40 years! —The preceding unsigned comment was added by 71.202.40.194 (talk) 06:48, 29 January 2007 (UTC).

Er... Poly-Si isn't really a metal, making the "M" is MOSFET a bit of a misnomer. The materials being used for compatibility with new high-k gate dielectrics are actual metals again. -- mattb @ 2007-01-29T13:25Z

JFET

the jfet symbol should be removed from this page as it is a significantly different device ZyMOS 18:48, 18 April 2007 (UTC)

I think it doesn't hurt, since they are clearly identified as not MOSFETs, but cousins thereof. Dicklyon 19:35, 18 April 2007 (UTC)

SAGFET plagiarism

This diff is where the plagiarized material on the invention of the SAGFET came in. It was the only wikipedia contribution of this IP user. If someone wants to take a look and summarize and reference the source site, it might be useful. Thanks User:Oli Filth for catching this. Dicklyon 02:40, 27 April 2007 (UTC)

Expert help needed

On Metal–oxide–semiconductor structure; please help fill in the outline with what you know. Dicklyon 20:59, 28 April 2007 (UTC)

Oooops! I started this article, and dropped it! I'll have to do some work on it (not sure when). Thank you for reminding me of it, and sorry for the mess!CyrilB 21:56, 29 April 2007 (UTC)

Subthreshold sensitivity to process variation

There is no doubt that the subthreshold region is exponentially sensitive to variations in threshold and oxide thickness. The impact this has on optimization is simply that a subthreshold circuit must be designed to support a huge variation in MOSFET behavior, which naturally means that the design cannot be pushed too far or it will suffer from poor yield. Is there any dispute over these matters? If so, what??Brews ohare (talk) 16:13, 19 November 2007 (UTC)

The sensitivity to Vth is greater in subthreshold only to the extent that the transconductance relative to Ids is greater. Either above or below threshold, threshold fluctuation comes in as a delta in Vgs-Vth, the surface potential that controls the current. Circuits do have to be designed to tolerate threshold fluctuation, as do above-threshold circuits; it's important in mirror ratios, but not so much in differential pairs, for example, just as in above-threshold analog circuits. The issue is not usually a yield issue, though; either the design tolerates a wide range of Vth fluctuation or it doesn't, in which case it has some badly controlled parameters. Designers are traditionally afraid of subthreshold because they haven't been taught to understand it, not because it's inherently much different or more sensitive than above-threshold circuits. Dicklyon (talk) 23:26, 19 November 2007 (UTC)

I'm unclear about the ratio argument. For example, g_m/I_D in subthreshold is independent of V_th: does that mean more tolerance to V_th variation than above threshold?? I hope I could figure all this out eventually, but maybe you could rephrase the remarks on subthreshold to be more accurate?Brews ohare (talk) 00:16, 20 November 2007 (UTC)

Yes, in some ways a well-designed subthreshold circuit can easily tolerate lots of threshold variation; the key is to control the bias current in transistors whose gm you care about. Doing so usually requires some mirrors, so big devices are likely needed in some places to keep the threshold fluctuation under control. Here are some places to look for things to say about it. Dicklyon (talk) 01:02, 20 November 2007 (UTC)

I'll take a look, thank you. Aside from its impact on signal processing, the Shukla reference suggests that the variation of power consumption with manufacturing variations can be an issue. The Srivasta reference suggest a modified worst-case design methodology is needed because worst cases are just too conservative with an exponential dependence. So besides my lack of understaning of the ratio argument, there may be other complications in subthreshold??Brews ohare (talk) 01:11, 20 November 2007 (UTC)

The key to controlling subthreshold power is to program currents, not voltages. The threshold becomes irrelevant over a wide range. Exactly how to do this is where the good tricks are. Dicklyon (talk) 04:05, 20 November 2007 (UTC)

Early Effect Terminology

I am concerned with the usage of the term "Early Effect" in the MOSFET article. This is a bit misleading as the term "Early effect" is meant to apply exclusively to BJTs and "channel length modulation" is generally a much more descriptive label. While some texts do allude to the Early effect due to the similar behaviour and notation (particularly allusions to the "Early voltage" in a MOSFET) it is not something attributed to James Early. More importantly, I have always found the term "Early effect" overly ambiguous and qualitatively void. I have, however, noticed that this terminology has also been used on the Early effect page as well and possibly on other pages. Thus it may be some ordeal to fix. So ultimately I just plan to inform the community and see if it is worth correcting. I suppose it just caught my eye due to it seeming something of an oversight in such a well developed article. Thanks for considering. (Vincent Baier, unregistered) —Preceding unsigned comment added by 129.21.137.68 (talk) 07:49, 8 April 2008 (UTC)

Self-Aligned Gate Technology

I think it would be beneficial to either add a section on self-aligned gates or add a link to the self-aligned gate page under the see also pages nd revise/add to it. Blewis87 (talk) 20:16, 10 April 2008 (UTC)

enhancement mode

please explain the reason/logic for naming the enhancement MOSFET in the article (and what is the difference between this kind of MOSFET and the depletion MOSFET). 62.219.54.250 (talk) 09:46, 15 June 2008 (UTC)

The enhancement-mode device doesn't conduct much at all at zero gate bias; a field from the gate enhances the conduction. A depletion-mode device does conduct at zero gate bias; a field from the gate depletes the channel of carriers to make it not conduct. The difference is really just whether the threshold is positive or negative; the fields I mention above are actually of opposite polarities. Dicklyon (talk) 06:11, 16 June 2008 (UTC)

Gate Capacitance

I don't know where to add this: " Gate of MOSFET is a capacitor to be charged and discharged. Typical effective capacitance is 2nF."1 Chendy (talk) 09:28, 25 April 2009 (UTC)

It might be useful to have a section on gate capacitance, since it's a key property of MOSFETs. But that source is way too narrow to be helpful. Typical values are from femtoFarads through picoFarads to nanoFarads, depending on geometric factors like width, length, and oxide thickness among other things. Dicklyon (talk) 14:49, 25 April 2009 (UTC)

History

Is the MOSFET a development of the Metal rectifier, analagous to a triode valve being developed from a diode valve? Biscuittin (talk) 20:08, 30 April 2009 (UTC)

No relationship; the "metal" in MOS is pretty irrelevant; the "oxide" (insulating latey) is key. Dicklyon (talk) 21:47, 30 April 2009 (UTC)

Etymology

I deleted some stuff that didn't make sense. If anyone knows what it was about, please restore it in an intelligible form. Rumiton (talk) 15:26, 30 June 2009 (UTC)

LED driver example

I think the circuit shown in File:Mosfet n-ch circuit.png is a bad example for MOSFET applications because there are simpler/similar LED driver circuits with better properties.

Such LED driver circuit would only work properly (that is, driving the LED at ~20 mA) if the voltage source is constant and the LED has a forward voltage drop fairly known. I mean, you can't use this circuit to test LEDs of several types and you must use a fairly exact voltage source in order to work as intended.

212.183.240.71 (talk) 15:34, 4 September 2009 (UTC)

Must be a candidate for the most overcomplex wiki page award...

Article goes into unbelievable levels of math, but nowhere does it state in clear-language what the device does, or what its fundamental characteristics and operating limits are. In fact, the statement "Each of these components can sustain a blocking voltage of 120 volts and a continuous current of 30 amperes." suggests to the reader an impossibly-high power rating, it being unclear that these two conditions cannot exist simultaneously for more than a very short time.

Agree with previous post that the LED driver is a poor example, not because it wouldn't work (it would) but because it is a pointless use of the device, the same result being achieved if the switch replaces the mosfet. A better example would be as a relay or motor-driver for low-current logic outputs. This would illustrate quite well the device's ability to control moderate or high currents with negligible input-loading, which is its key advantage over bipolar transistors. --Anteaus (talk) 13:49, 17 October 2009 (UTC)

Although the amount of math is not the worst problem, I agree that this is a severe case of WP:OBVIOUS. I added a few words to the lede. The article needs graphics to explain the channel. I added a figure from Commons, next to that very long table of contents. /Pieter Kuiper (talk) 15:05, 20 November 2009 (UTC)

And typically, User:Dicklyon immediately finds fault. Being the expert, he changes "no conduction" to "little or no conduction" with the admonition "don't deny subthreshold conduction" - as if I had deleted the section MOSFET#Higher subthreshold conduction. I reverted parts of his edits, because the introduction is about trying to explain basic operation, not about showing off one's expertise to colleagues. /Pieter Kuiper (talk) 16:38, 20 November 2009 (UTC)

I didn't add anything about subthreshold conduction; just trying to make it correct by not denying it; it was wrong before where it said "...below the threshold for making a conductive channel; there can be no conduction...", so I made it right with a small change. And the electrons pretty much all come from the source in normal operation (or from the source and drain when the transistor is not in saturation) (see these books). The idea that the mobile charges can come from somewhere else, like they do in a MOS capacitor, is hardly applicable to the transistor. Furthermore, the idea that the channel becomes "n-type" seems like an unusual way to describe inversion; what's inverted is the carrier density ratio, not the doping type; but there are a few books that do use your terminology there, so I'll leave it alone for now. Dicklyon (talk) 01:46, 21 November 2009 (UTC)

Mistake in equation for output resistance

Shouldn't the MOS output resistance (ro) just be lambda/Id? That's the equation given in both references and -Protective1 (talk) 00:59, 15 March 2010 (UTC)

The formula should be ${\displaystyle r_{OUT}={\frac {1}{\lambda I_{D}}}}$. r_out is the inverse of g_ds where ${\displaystyle g_{DS}={\frac {\partial I_{DS}}{\partial V_{DS}}}}$ . Caragpietro (talk) 19:25, 13 April 2010 (UTC)

Parasitic drain-source (body-source) diode

There needs to be discussion of the purpose of the embedded parasitic DS (body-source) diode. —Preceding unsigned comment added by Nasukaren (talk • contribs) 00:34, 24 August 2010 (UTC)

Wrong picture

I would to you take a look at this image, where channel, at VDS=0.6, is located near source AND EVEN near drain. But if it so, common pictures like this are wrong, because channel should be located, even in saturation, not only near source but even near drain. Is my argument correct? --Lenore (talk) 10:20, 10 September 2010 (UTC)

Redundancy and Misplaced Pages style

It's quite redundant to say a "<foo>ish <bar> is a type of <bar>" (or worse yet, "... is a <bar> that is <foo>ish"). If the reader is minimally sentient, this is obvious, and if the reader is not sentient, it's not part of our target mandate anyway. Misplaced Pages's resources are indefinite, but the reader's lifespan is short and valuable; let's not waste it. --Wtshymanski (talk) 14:29, 10 January 2011 (UTC)

Yes, I realize that redundancy is problematic. However, please put yourself into the position of a non-technical reader reading the introduction. If you read a word monster like "metal–oxide–semiconductor field-effect transistor (MOSFET, MOS-FET, or MOS FET)", and have never heard of a "transistor", you will probably not realize that a MOSTFET is a type of transistor, thus the duplication. As a compromise, I wikified the term transistor (a link to "transistor" was missing in any case). Can you live with that? Sebastian (talk) 23:02, 10 January 2011 (UTC)

One link per paragraph is usually enough; just how clueless do we need to assume the reader is? --Wtshymanski (talk) 02:12, 11 January 2011 (UTC)

Ah,sorry,didn't see the link further down. BTW, could you please tone down your rethoric a bit? We're not in kindergarten here :-/. Thank you.Sebastian (talk) 22:04, 11 January 2011 (UTC)

You revert "poo" out of enough articles in a day, and you're in kindergarten. MIT this isn't. --Wtshymanski (talk) 22:24, 11 January 2011 (UTC)

Indeed! Sometimes, like Elliot on SVU, I just want to put away the perps, or worse, instead of AGF. Dicklyon (talk) 01:57, 12 January 2011 (UTC)

Elliot is a model of grandmotherly kindness; my impulses tend more to those of Ellen Ripley. It's the only way to be sure. --Wtshymanski (talk) 14:34, 12 January 2011 (UTC)

Dubious section

The section MOSFET#Advantages_of_BJT_over_MOSFET needs to be removed, or updated based on modern sources. These differences between MOS and BJT have pretty much gone away in the last few decades. Dicklyon (talk) 17:04, 27 February 2011 (UTC)

Undefined term

Unless I'm missing something, the term "V subscript T" (sorry, I haven't got to grips with entering maths yet) as used in the section "Cutoff, subthreshold, or weak-inversion mode" is currently undefined. I think it should equal kT/q (and then I suppose k, T and q would need to be defined as well). This may well be supported by reference 4, but I don't have access to the relevant page of that book. It's also in "Mosfet modeling for VLSI simulation: theory and practice" by Narain Arora, for example. Richard J Price (talk) 11:04, 4 April 2011 (UTC)

You are correct, it is the thermal voltage: ${\displaystyle V_{T}=kT/q}$; these variables are somewhat more well-known constants and absolute temperature; are they perhaps already defined in the article? Dicklyon (talk) 06:34, 5 April 2011 (UTC)

OK, I've added the definition of ${\displaystyle V_{T}}$ but none for k, T or Q, since as you rightly say these are more well-known. (I can't find them defined elsewhere in the article, incidentally.) Richard J Price (talk) 12:36, 5 April 2011 (UTC)

Suggest merge

Over at 2N7000 there's a bunch of MOSFETs being discussed; it would seem to be to be a natural merger to th is article under "Popular devices" or some such heading; it would give the parts list a context. --Wtshymanski (talk) 20:02, 17 April 2011 (UTC)

It's not clear to me how it would help either article to have a section on a few particular popular hobbyist small-signal switch MOSFETs here. That would be a magnet for listing every part anyone cares about. At least with a separate article, there are some criteria like notability and relationships of the notable part to other parts as found in reliable sources to help control the proliferation. I think this proposal works against your stated goals. Dicklyon (talk) 01:53, 18 April 2011 (UTC)

Parts aren't usually made for the hobby market, which must be a fairly insignificant part of the electronics business. ( We don't know from the 2N7000 article how many are made or sold each year in any case.) The 2N7000 article has very little content and a recitation of 3 or 4 popular exemplars giving their data sheet parameters would take up little space here and would avoid repeated explanation under the 2N7000 article. It would be more appropriate to discuss a collection of part numbers under a collective title, rather than lump them under one randomly selected part number. --Wtshymanski (talk) 03:09, 18 April 2011 (UTC)

If I see no support for this proposal soon, I'll back it out. Dicklyon (talk) 05:13, 21 April 2011 (UTC)

They are not important enough...to list...in an article about MOSFETs, but they are important enough to have their own articles. Right. that settles it, I'm not smart enough to edit this encyclopedia. --Wtshymanski (talk) 13:33, 21 April 2011 (UTC)

Break up Circuit Symbols Box/Table

Can someone proficient with the format code break up the MOSFET#Circuit_symbols box with the 10 graphics so the two JFET symbols occupy their own box? (essentially split the single box into two boxes so that JFETs occupy one and MOSFETs occupy the other). It's currently confusing boxing them together for myself trying to learn about MOSFETs, when JFETs are a separate device.

Why are you confused by having JFETs also shown with the various MOSFETs? Dicklyon (talk) 00:15, 1 November 2011 (UTC)

It's not having them shown together that I have an issue with. It's having them shown in the same box. This implies to my brain that JFETs are a type of MOSFET, which they are not. Zerohourrct (talk) 02:15, 1 November 2011 (UTC)

I don't see the problem. The text before and in the box make it pretty clear that they are not MOSFETs. Dicklyon (talk) 02:20, 1 November 2011 (UTC)

Description and corresponding letters of source, gate, and drain

A total newbie to electircal engineering here. I was working with a MOSFET and assumed G was ground, not gate. Something indicating the meaning of S, G, and D would be hugely appreciated. — Preceding unsigned comment added by 68.116.170.225 (talk) 20:36, 23 January 2012 (UTC)

Agree. This is an excellent article but it lacks some very basic information that the general public would want to know. Somewhere in the lede there should be something like this.

A MOSFET is a three terminal electronic device, the three terminales being the gate (G), source (S) and drain (D).

Or anything similar to that. 64.40.60.149 (talk) 05:53, 19 March 2012 (UTC)

MOSFET a four terminal device

This reversion suggests "rv substantial uncited rewrite. A claim that MOSFETs are generally four-terminal devices and only three- in the exceptional case is going to need a serious citation." is misconceived. The reverted statement is:

Although the MOSFET is a four-terminal device with source (S), gate (G), drain (D), and body (B) terminals, the body (or substrate) of the MOSFET often is connected to the source terminal, making it a three-terminal device like other field-effect transistors.

This statement agrees that the S-B connection is commonly made, and does not claim that "MOSFETs are generally four-terminal devices and only three- in the exceptional case". That is, in fact, completely contrary to what is said. Brews ohare (talk) 17:12, 21 March 2012 (UTC)

It might be added that there is no doubt that the MOSFET is a four-terminal device, regardless of how it is used. Brews ohare (talk) 17:14, 21 March 2012 (UTC)

This might stand within the body of an article, but I don't believe it belongs as the second sentence of the lead. A typical reader isn't going to know much about MOSFETs, but they will probably know them as the typical three-terminal device. If pretty much the first thing we say is that MOSFETs are actually four-terminal devices, then that's going to create more confusion than clarity.

Secondly, is this true as such a broad and general statement? There are many, many sorts of MOSFET around. Some are individual packages, most are in ICs on a shared substrate, others are peculiar variants for high power use. Does this broad statement apply equally to all of them? Of course, there's also the question of citing it. Andy Dingley (talk) 17:26, 21 March 2012 (UTC)

Some diagrams in the article show all four terminals.

Yes, the broad statement is universally true: one cannot obtain the field effect (semiconductor) without a body connection, which can be attached to the source, of course.

A citation could be found: I'd guess that it is somewhere in the article already inasmuch as many of the diagrams trhere show the four terminals. Brews ohare (talk) 18:00, 21 March 2012 (UTC)

So what about the first point?

Additionally, if " cannot obtain the field effect (semiconductor) without a body connection" (by which I assume you mean that two of these four terminals must always be commoned), then is there any real scope for ever calling this a four terminal device? Andy Dingley (talk) 18:08, 21 March 2012 (UTC)

Andy: I have added a source from the well-known Berkeley group under Chenming Hu. There is no requirement that any two terminals be connected together. There is a requirement that a voltage drop be made to exist between the gate and body.

I don't find it confusing to state the existence of four terminals. That is what the structure is.

If anything, it's more confusing to start with a three-terminal structure that doesn't correspond to the physical facts, and then later introduce a fourth terminal.

If a reader arrives accustomed to the three-terminal operation, they are immediately put on board by the statement that the source and body are commonly connected. I assume that makes it clear that when two terminals are connected to each other only three terminals appear in electrical diagrams.

There is a section in the article on body effect that might clarify the substrate connection.

Hope we are now on the same page. Brews ohare (talk) 18:20, 21 March 2012 (UTC)

Brews is not incorrect, but I think maybe the way I had put it was better received: "Like other field-effect transistors, a MOSFET is usually a three-terminal device with source (S), gate (G), and drain (D) terminals; the substrate of the MOSFET is sometimes connected to the source terminal, and is sometimes a separate fourth terminal." It's a matter of point of view on what the "device" is, and what a "terminal" is. In chip design, you generally have to treat them as 4-terminal devices, but in discrete transistors, they're usually thought of as 3-terminal devices. That's life. And it is possible to have field-effect devices with only three terminals, controlled only by gate relative to source, with no bulk (e.g. certain JFETs). Dicklyon (talk) 03:55, 22 March 2012 (UTC)

Brews' last point is rather what I was thinking about. If a large number of MOSFETs are formed on a shared substrate, then is that substrate connected to the Source terminals (and by implication, all the Sources are thus commoned!) or is it instead that the body substrate has to be held to some separate potential, such that the potential across all of the Gate / Body junctions is appropriate, but that the Sources don't need to be commoned? Andy Dingley (talk) 11:08, 22 March 2012 (UTC)

Andy, these are technical details that vary with the application. The basic point to be made is that these choices are predicated upon there being four terminals whose use can be adapted to the application. Brews ohare (talk) 15:21, 22 March 2012 (UTC)

This "vary" is what I'm getting at. If there is variation (and for shared substrates, I suspected that there was), then I don't think we can place such a blanket statement, so early in the lead. Andy Dingley (talk) 15:46, 22 March 2012 (UTC)

Andy, what does this boil down to? It seems that you feel the statement that a MOSFET is a four-terminal device, while accurate, involves counting to four instead of counting to three, and so is too complex and should not be mentioned early in the article. Your reasoning, though not stated so baldly, is that a majority of readers will come to the article with the idea that the MOSFET is a three terminal device, and will be floored by the idea that it has, in fact, four terminals. The immediate bridge in the initial statement, that the source and body are frequently tied making the four terminals into three, is so convoluted that these readers simply will be left perplexed and leave the article in a daze of confusion. Is that your perspective? Brews ohare (talk) 16:52, 22 March 2012 (UTC)

Not really. If it's true that all (and I mean all) MOSFETs are 4-terminal devices with the Body & Source strapped together, then maybe there's reason to put this so bluntly, so early. However I'm still not convinced that they are - in the case of shared substrates across many devices. They obviously have commoned Bodies, so AFAICS this would also imply that all such MOSFETs would also have their Sources commoned, which I don't believe to be the case. The Body needs to be kept at a certain potential relative to the Gate. For an individual device, the easy way to do this is to strap it to the Source. However the fundamental requirement is just to manage that substrate potential (which can be done as a one-off across a whole die of devices), not specifically to tie the Source.

I also have a slight concern about the phrasing of "four terminal". Wouldn't it be clearer if we had some other term here for the contacts, and so could keep "terminal" for the connection that goes outside the package. Andy Dingley (talk) 17:02, 22 March 2012 (UTC)

Thanks for the elaboration. The word "contact" could be used if you like that better than "terminal". Your statement:

"If it's true that all (and I mean all) MOSFETs are 4-terminal devices with the Body & Source strapped together, then maybe there's reason to put this so bluntly, so early."

is a bit confusing to me. The way I'd put it is:

"All MOSFETs are 4-terminal devices. In many applications the Body & Source are strapped together."

It seems you wish to involve the early discussion in distinctions between discrete devices and those in ICs. That is something I'd relegate to later in the article. IMO the most accurate and the cleanest way to proceed is to introduce the 4-terminal device in its full glory and then proceed to its various ramifications having presented the general concept. An evolution from the general to the particular. Brews ohare (talk) 17:46, 22 March 2012 (UTC)

For the lead, I don't think we need to mention either. The MOSFET has a function (to be an active device or transistor) and it has a primary means of operation (the channel production). Anything beyond this, such as fabrication, or the need to bias the substrate, is secondary. I don't think secondary things need to go in leads. Andy Dingley (talk) 17:59, 22 March 2012 (UTC)

Andy, I as far as I know, "all" is correct, though one could imagine MOSFET structures without a separate body (e.g. a thin channel region between commoned gate terminals, more like a JFET but with insulating layers). It is certainly NOT the case that in chips were all share a body that they would also share source contacts; you wouldn't be able to make logic circuits, or much else, in that case. Typically in CMOS about half of device sources connect to the body terminal, but in some chips, none do, like in old NMOS chips with substrate bias, and in some CMOS with regulated well potentials. The fact that they are four-terminal devices is important, well known, and universal. So let's work out the best way to say that. Per Brew's remark, yes, it's true that some readers will be baffled and put off when they read four and they see three in every MOSFET they look at, which is why I had said it in a way that would introduce that surprise more gently. We could go back to not mentioning terminals in the lead; I had added that per a talk page request (which asked for an explanation of the three terminals, from a guy who didn't know about four). Dicklyon (talk) 18:02, 22 March 2012 (UTC)

Here is a Google book search and here's another. The "four-terminal" approach to MOSFET is very common. Brews ohare (talk) 18:22, 22 March 2012 (UTC)

Here is the corresponding search for the three-terminal case. Not as many, but within a factor of three to four anyway. Dicklyon (talk) 23:28, 22 March 2012 (UTC)

How it works

Brews, I see you're working on the description of how it works. I never liked that idea that the voltage from gate to substrate is the main or only thing that matters in terms of channel creation; I understand that it does control inversion, accumulation, depletion region depth, etc. in a MOS cap, but in a transistor that has a source, the mobile channel charge comes from the source, not from the substrate. As you know, you can control the source–drain current by tying the gate and substrate together and moving the source relative to those (within limits, as you don't want to forward bias your isolation junctions much), effectively using the substrate as a "back gate". So the description you just edited is still not very satisfying in that regard. Looking at it another way, if you fix the S, G and D voltages, and look what happens when you move the B voltage, it's exactly opposite of what is suggested by saying that "a voltage drop between the oxide-insulated gate electrode and its substrate induces a conducting channel." In other words, it's the surface potential (relative to the source) that most affects the current, not the drop from gate to substrate. Yes? Dicklyon (talk) 23:41, 22 March 2012 (UTC)

Hi Dick: A full explanation would be a bit much in the intro. I don't think a simple form of words covers the matter. The full explanation requires the concept of quasi-Fermi levels. The bulk has one Fermi level and the source and drain (assume they are shorted for argument's sake) have theirs. The two are separated by the reverse bias between source and substrate.

For a long channel device, where the pn-junction depletion regions are small compared to the source-to-drain separation, the bulk Fermi level controls matters at midchannel and it looks like an MOS capacitor. However, as the inversion layer becomes established, and extends all across the interface, the Fermi level of the source and drain set the population of the inversion layer.

So there is a hand-off as the inversion layer strengthens. If there is no reverse bias and the two Fermi levels are the same, the MOS capacitor analysis continues to hold good. If now a reverse bias is applied from source to substrate, the Fermi level in the inversion layer drops, so threshold for formation of the full inversion layer is delayed to larger gate-to-substrate voltages when reverse bias is present.

The hand-off is muddier for a short-channel device, where all three electrodes interact directly with the full depletion layer, as well as via the channel.

How would you like to handle this matter? Brews ohare (talk) 05:39, 23 March 2012 (UTC)

I'd like to say less in the lead; I'd omit the idea of channel inversion, and if we mention gate voltage, make it with respect to source, not bulk. I'm not sure what you mean by "the bulk Fermi level controls matters at midchannel." Isn't the mobile charge there mostly controlled by what happens at the source? Dicklyon (talk) 06:06, 23 March 2012 (UTC)

Dick, I believe your intuition is on the wrong track. So long as there is no voltage V_SB and no V_DB, the device behaves like an MOS capacitor and it is the gate-to-substrate voltage V_GB that decides whether there is a channel. If there is a channel, say electrons, they can move freely between the channel and the source or drain; the Fermi level is the same all the way across. However, if we make V_SB ( = V_DB) a reverse bias, it lowers this common Fermi level compared to the Fermi level in the bulk. To first order the surface potential is pinned (unaffected at a fixed value conventionally taken as 2φ_B) so the field in the oxide is unchanged by the reverse bias. But the drop in population of the channel means the charge balance is upset. To satisfy Gauss' law, the oxide field is now balanced by a larger negative depletion layer charge to compensate for the loss of negative channel charge. In math:

${\displaystyle Q_{I}+Q_{D}=\kappa \epsilon _{0}(\phi _{G}-\phi _{S})/t_{ox}\ ,}$

where φ_S is pinned at 2φ_B, Q_I = inversion layer charge, Q_D = depletion layer charge. This equation is the same as in the MOS capacitor, but Q_I is not related the same way to φ_S, but is reduced by a factor exp(qV_SB/kT).Brews ohare (talk) 15:22, 23 March 2012 (UTC)

This Boltzmann factor is an exaggeration: one has to do a careful calculation of the effect of the change in Fermi level. Brews ohare (talk) 16:21, 23 March 2012 (UTC)

So there is nothing misleading in the intro statement for the simple case of no reverse V_SB. The charge in the channel has nothing to do with the source until a reverse bias is applied. Brews ohare (talk) 15:22, 23 March 2012 (UTC)

But in the region where the channel is getting charge from the source (that is, any region in which there is a controlled current), the V_gs is what matters most, and the bulk voltage V_bs affects current in the same direction that the gate voltage does, whereas looking at V_gb as controlling suggests that the bulk would work in the other direction. Dicklyon (talk) 15:27, 23 March 2012 (UTC)

Dick: The oxide field can be related to V_GS, but that is possible only when the channel is present. Otherwise, the oxide field is given as I have indicated in the Gauss' law equation above. So if we are interested in the mechanism behind formation of the channel, we have to go to the Gauss' law equation at midchannel and leave the source out of it.

I am not sure what you are saying about the substrate bias. I imagine we agree that reverse bias on the source expands the depletion layer. When there is a channel, V_SB affects the Fermi level all through the channel and lowers its population. The expansion of the depletion layer midchannel then stems from the Gauss' law equation above with Q_I modified by the source V_SB. If there is no channel, then V_SB has no effect at all and Gauss' law midchannel is as given, but with Q_I=0.

The effect of the source on midchannel is absent until the channel forms to extend the source's influence the full width of the device. If one wants to describe the field effect that forms the channel, one cannot use the V_GS formulation because it works only after the channel forms. Brews ohare (talk) 16:06, 23 March 2012 (UTC)

A brief look suggests you might find this source helpful. Brews ohare (talk) 17:20, 23 March 2012 (UTC)

Brews, I think I get all that, though I'm certainly not the MOS expert that you are. But what I'm saying is that concentrating on channel formation gives the wrong impression in important cases. In particular, consider the common case of the MOSFET in saturation, (so we can ignore the drain), with a small nonzero current I_ds. Now, what happens if you change the bulk potential, relative to the other three terminals? Say you move the voltage up, in an NFET. This reduces V_gb, so would tend to make less of a channel. But the effect is that it increases the current, since it raises the surface potential and allows more electrons to enter from the source. This is the sense in which I think concentrating on channel formation is misleading. The source current is controlled not so much by the existence of a channel, but by the relative barrier height that allows electrons to enter. Admittedly, my thinking on this may be more relevant in the subthreshold region where the surface potential is most relevant, and where there is perhaps no channel in the sense that you mean. Above threshold, the bulk, or "back gate", continues to affect the current in the same direction that the gate does, not opposite as would be suggested by V_gb being the relevant parameter. Dicklyon (talk) 17:33, 23 March 2012 (UTC)

The notion of barrier height can be applied in subthreshold, but it does not apply elsewhere. Of course, subthreshold is a very special bias regime, and most circuits don't use the device in that mode. The notion that a barrier limits the current is just not true in normal operation, where the channel behaves like a resistor carrying a current dependent upon V_DS and a conductance dependent upon Q_I. A barrier limitation is a digression in this context.

I simply don't grasp the counterintuitive notion that V_GB provides the wrong dependence. I think you are ignoring the pinning of the surface potential in strong inversion. The oxide field is therefore fixed when V_SB is varied, and the increase in V_GB is not due to any change in oxide field but due to the increased depletion depth forced by Gauss' law when Q_I drops. The notion that varying V_B alters the surface potential and thereby affects Q_I and the current is incorrect outside of subthreshold. It is the Fermi level shift due to V_SB that affects Q_I. Brews ohare (talk) 18:43, 23 March 2012 (UTC)

Brews, I realize that you don't have much experience with transistors been used in the subthreshold region, but it's certainly not rare or unusual (and at the drain end, it's always in subtreshold if in saturation, so the resistor model is in applicable in that typical region). My own experience is more with micropower circuits (including substreshold transconductance amplifiers and such) and image sensors (with subthreshold conduction in overflow/antiblooming transistors and other places), and in 4T "loadless" SRAMs with subthreshold load currents. But if you don't want to look at that region, consider near and above threshold, where substrate bias can be thought of as a way to adjust threshold. More substrate bias (lower bulk voltage for an nFET) relative to the other terminals raises the threshold voltage, thereby reducing the current, even though it increases V_gb and increases the channel formation, because it also increases the barrier that electrons in the source need to get over to enter the channel. So lower the bulk voltage lowers the current, contrary to what the channel-formation model suggests. Yes? Dicklyon (talk) 18:01, 25 March 2012 (UTC)

Dick, thinking about this, I came to the conjecture that perhaps we are looking at different electrodes as the reference.

One can look at this from various perspectives: for instance, imagine the gate and source-drain fixed in an nMOS device. The source is reverse biased by driving the substrate negative, V_SB > 0. The Fermi level in the channel drops and Q_I goes down. The oxide field is fixed, so Q_D increases in magnitude. The potential drop across the depletion layer goes up to about 2φ_B+V_SB. The surface stays at 2φ_B, the oxide field at (φ_G-2φ_B)/t_ox. Alternatively, the substrate could be held fixed and the source and gate increased by V_SB, which is the same situation, but using a different electrode for reference. In this case, if the gate is now brought down to V_G from V_G+ V_SB, we obtain a situation where the reverse bias on the source is obtained by positively biasing the source while keeping the gate and body fixed. Of course the drop in gate voltage means the oxide field goes down. If the channel is still there, its population drops while the depletion layer remains enlarged corresponding to 2φ_B+V_SB. Brews ohare (talk) 16:07, 24 March 2012 (UTC)

That's not the issue. See above. Perhaps consideration of a double-gate MOSFET with no bulk connection will be a useful analogy to explain what I mean about the back gate working in the same direction as the gate, not opposite to it. Dicklyon (talk) 18:01, 25 March 2012 (UTC)

Dick, I don't understand you, and you don't understand me. I don't think there is a remedy. Brews ohare (talk) 03:20, 26 March 2012 (UTC)

In any event, this discussion concerns the influence of source-to-substrate bias, which has no part in the introduction, and does not impact the reference to the field effect as the underlying mechanism underlying channel formation. Brews ohare (talk) 04:28, 26 March 2012 (UTC)

My point is that focusing on "channel formation" also doesn't belong in the lead. Do you agree at least that in an nFET, raising the bulk voltage (relative to constant voltages of the other three terminals) will tend to increase the current, not decrease it? And do you agree that raising the bulk voltage reduces the "voltage drop between the oxide-insulated gate electrode and its substrate"? And that that sounds like it causes there to be less of a conducting channel? In fact, in strong inversion, the bulk potential does very little, due to screening by the charge sheet in the channel, right? So the conduction is pretty much controlled by Vgs, and Vgb does very little, right? Dicklyon (talk) 05:23, 26 March 2012 (UTC)

Let us begin by clarifying what "increasing" the bulk voltage means. In my mind it would mean forward biasing the source and drain junctions with the substrate. That is a mode hardly every employed in circuits. Is it what you mean? Brews ohare (talk) 12:12, 26 March 2012 (UTC)

To reply about the field effect, assuming zero bias across source-substrate and drain-substrate pn-junctions, the analysis at midchannel along a vertical line from the substrate to the gate is identical with that in a 1-D MOS capacitor in every respect. Brews ohare (talk) 12:25, 26 March 2012 (UTC)

Yes, that is the direction I meant, but I think I already specified that I meant not so much as to forward-bias the S/D junctions. And I meant from whatever starting point you like, which may have been a negative potential. And I meant the linearized effect, so the direction could equally be the other way, with the opposite result. That is, taking the substrate more negative will reduce the current, even though, I agree, the MOS cap analysis suggests that it will make more of a channel. An example of using the back-gate as an explicit input, with the direction of effect that I'm describing, is here. And, risking repeating myself for clarification, I'm not arguing that anything you said about channel formation is wrong. What I'm arguing is that that doesn't give you much insight into the current through the device, which is much more contolled by Vgs, and depends on Vbs in the direction opposite to what a focus on Vgb would suggest. Do you agree, or disagree, on the direction in which varying the body voltage relative to the other three terminals will affect the current? That is, that moving the body in the direction of making more of a channel (lower voltage in the case of an nFET) will reduce the current? And that moving the body up, making less of channel, will increase the current? Dicklyon (talk) 16:45, 26 March 2012 (UTC)

As I agreed earlier, once the inversion layer is formed, it is fine to think in terms of Vgs, because the oxide field all along the channel, including mid-channel is related to Vgs. It is the oxide field that supports the channel and decides its strength. Supposing that the source and drain are not reverse biased and Vgb is increased, then the current does increase all the way from below threshold to above it, as the field effect suggests, so I'd guess you have no problem in this case?

So the quandary (?) arises only when reverse bias is applied to the source. Of course, Vgs doesn't change, so it is hard to make the case that Vgs is the controlling factor in this situation. So to handle this case you'd like to see the Vbs effect as a field effect from the substrate as a gate, making a kind of symmetry with the Vgs case. Is that right?

With an inversion layer present, for an nMOS device, applying a negative substrate voltage increases the depletion layer charge and lowers the channel density. Vgs is held fixed, so the total drop from gate to body Vgb increases although the current goes down. Your perspective upon this is that the field effect would suggest that a large Vgb means a larger current, not a smaller one, so you'd say the field effect from the gate is the wrong way to look at it. I guess that is what you are aiming at?

In the reverse Vbs case, my preference is to maintain the notion of the field effect from the gate, that is, control by the oxide field, and point out that Vbs reduces the Q_I via a Fermi level shift, so the oxide field expands the depletion layer according to the field effect with reduced Q_I. The effect of Vbs from this stance is about Vbs sucking charge out of the channel into the source.

So, I guess you'd like to avoid the Fermi level argument and find an argument that treats the gate and substrate similarly. I suppose the symmetry of that idea appeals to you. If I'm on the right track, maybe we can continue? Brews ohare (talk) 18:08, 26 March 2012 (UTC)

You're right, we're not going to understand each other. Did you look at the paper I linked? Dicklyon (talk) 04:04, 27 March 2012 (UTC)

Dick: The paper you refer to uses the device in saturation and varies the threshold voltage slightly with a forward substrate bias. The analysis applies assuming the channel is present, so its bearing upon channel formation is nil. This mode of operation is atypical. It will inject current into the source and drain from the substrate, because the junctions are forward biased, and so the device carries a "back-gate" current, unlike the normal front gate that is insulated, and causes no forward bias of the junctions.

Questions:

Do you agree that the standard MOS capacitor analysis for the field effect applies midchannel if Vsb, Vdb are zero? Vgs plays no role in this analysis, which is in terms of Vgb.

Do you understand the standard Fermi level analysis of Vsb effects as I've described them?

Why do you want to introduce Vsb ≠ 0 operation in the introductory paragraph? It seems to me that Vsb effects should be presented in the body-effect section, and if that is interesting, the standard Fermi level approach can be compared with alternatives there. Brews ohare (talk) 12:40, 27 March 2012 (UTC)

Brews, yes, I agree with the analysis for channel formation midchannel (but if I understand the words "inversion" and "channel" it's only inverted, or only a channel, when there are electrons in the channel, i.e. when the transistor is in an ON state, which is very dependent on source voltage). I sort of understand the Fermi level analysis, and have no problem with that. And I am NOT suggesting we add any of these complications to the lead. Rather, I'm suggesting that we simplify the lead by removing the stuff about Vgb and channel formation.

Your interpretation of body effect as a slight shift of threshold is entirely consistent with what I've been saying about the direction in which body voltage will affect current, which is in the opposite of the direction in which it affects channel formation. The current wording here is very confusing:

In enhancement mode MOSFETs, a voltage drop between the oxide-insulated gate electrode and its substrate induces a conducting channel between the source and drain contacts via the field effect. The term "enhancement mode" refers to the increase of conductivity with increase in a field that adds carriers to the channel, also referred to as the inversion layer.

What field adds carriers to the channel? The carriers only come from the source, and increasing the field by lowering the body voltage works against that. And this "increase of conductivity" concept is only applicable in the space-charge-limited (strong inversion) region, so it ignores the whole important weak-inversion region where charge travels by diffusion, not by a drift limited by conductivity. So, I think your approach is somewhat traditional, but thereby is only applicable to the strong-inversion ON region, and even there is misleading about how body voltage will affect current (by suggesting that lowering body voltage to a more negative voltage will increase conductivity, which sounds like it should increase current, when it actually decreases the current, by raising the threshold in your language). Dicklyon (talk) 17:01, 27 March 2012 (UTC)

Dick, I'll pick out a few points for reply:

if I understand the words "inversion" and "channel" it's only inverted, or only a channel, when there are electrons in the channel, i.e. when the transistor is in an ON state, which is very dependent on source voltage

Yes the channel exists in the ON state. In pMOS the channel has holes, in nMOS electrons. Assuming source and body are grounded, the existence of the channel depends only on the gate voltage, and the behavior is the same as the MOS capacitor, where there are no source or drain electrodes. So to say the channel depends upon the source voltage is incorrect in this situation.

What field adds carriers to the channel? The carriers only come from the source...

By field, oxide field is meant. The carriers in the MOS capacitor come from SRH-generation in the depletion layer, as there is no source. When the oxide field increases, it lowers the conduction band so more of it is available for population by electrons. When a source is present, electrons still can be generated by the SRH mechanism, but as soon as the channel forms, it is much faster to supply them from the source.

this "increase of conductivity" concept is only applicable in the space-charge-limited (strong inversion) region, so it ignores the whole important weak-inversion region where charge travels by diffusion

This statement is not correct. The "increase in conductivity" is a continuous process, continuous with increasing oxide field, from depletion through weak inversion to strong inversion, just as in the MOS capacitor. The conductivity depends only on the channel population, and not upon either the generation mechanism or the transport mechanism from source to drain.

...is misleading about how body voltage will affect current (by suggesting that lowering body voltage to a more negative voltage will increase conductivity...

There is no reason to drag body voltage into this matter, as the channel formation is well-described by the field effect, which is controlled by the gate alone. If you do want to include a discussion of Vsb, then that can be done, but it is a digression so far as channel formation is concerned.

If Vsb is to be discussed, that can be done, but it is a separate issue from the field effect from the gate that controls channel formation. If you were to write down the 1-D Poisson equation at midchannel (the equation describing the field effect), the charge term consists of minority carriers and depletion layer charge. The minority carrier density is the same as for the MOS capacitor, but reduced by a factor depending upon Vsb. That factor stems from the changed Fermi level of minority carriers. It is not an electrostatic effect; the Fermi level is a form of electrochemical potential. The electrostatics are altered midchannel however, because the minority carrier charge term for a given oxide field is decreased due to this Fermi level shift. As a result the calculated band bending across the depletion layer corresponding to a given oxide field from the 1D Poisson equation will be increased, and the depletion layer is wider for a given oxide field when Vsb ≠ 0. That makes the sum of charges per unit area, Q_I + Q_D, the same for the same oxide field, regardless of Vsb, as required by Gauss's law. Brews ohare (talk) 21:11, 27 March 2012 (UTC)

If you doubt my statements, take a look at the book I suggested above. Or look at Tsividis. Brews ohare (talk) 21:31, 27 March 2012 (UTC) The Fermi level shift under reverse bias is discussed in P–n_diode#Reverse_bias for the pn-junction.

More on how it works

a header to break up the long commentary here

Most of your statements I don't doubt. But let me be clear: I'm not proposing we talk about the body voltage in the lead; quite the opposite: I'm saying we should take it out of lead, where it appears in "a voltage drop between the oxide-insulated gate electrode and its substrate".

The part of what you're saying that still confuses me is about what happens when the source and drain voltage are too high, so they take charge out of the channel, but don't put it in. Then the slow carrier generation will never make much of a channel, as the charges will exit as quickly as they are generated; inversion won't happen, even though the surface potential would happily accommodate carriers there, and the voltage that you think of as producing a conductive channel won't do so. Even at mid-channel, if the source voltage is too high, you'll get no channel, because all your mobile carriers will get away quickly. Right? In that sense, the stuff about channel formation and conductivity seems like just a conventional fiction, not very useful to understanding the current in any region other than strong inversion, and even that is determined more by the source than by the voltages that cause "inversion". I was never in the habit of paying attention to that conventional fiction, since I was working in weak inversion, where it was more troublesome than helpful. The model in the appendix of Carver Mead's Analog VLSI and Neural Systems worked better for that domain, where the back-gate effect is effectively linear and just like the gate in terms of how it modulates the current by moving the barrier to electrons entering the source. Dicklyon (talk) 05:02, 28 March 2012 (UTC)

In explaining the "field that adds carriers to the channel" you had to assume that the source is grounded. This is my point; it's Vgs that mostly matters, in terms of getting electrons into the channel. Suppose you've got source and body at ground, and gate at just below threshold, so you have little or no inversion later, not much charge getting into the channel. Can you then increase the conductivity by increasing the "voltage drop between the oxide-insulated gate electrode and its substrate" by lower the substrate to a negative voltage? No, you can't; that will increase Vth and turn the device more OFF. The idea the the "voltage drop between the oxide-insulated gate electrode and its substrate" is what makes the channel conduct fails, goes in the wrong direction, if what you're moving is the body relative to the other terminals. On the other hand, if you increase the "voltage drop between the oxide-insulated gate electrode and its substrate" by raising the gate potential, you do increase the current; but it's mostly because you increased Vgs. Or at least the usual way of thinking about Vgs seems more consistent than thinking of Vgb as the controlling item. Of course, you need enough Vgb to get a depletion region, or the electrons from the source won't find a suitable place to go. But you need the source to supply the electrons, or you're not going to get a channel, unlike in a MOS cap, where there's no drain to suck off the carriers that are thermally generated. Dicklyon (talk) 05:15, 28 March 2012 (UTC)

Hi Dick: Let me repeat a few of your remarks and respond to them.

"The part of what you're saying that still confuses me is about what happens when the source and drain voltage are too high, so they take charge out of the channel, but don't put it in. Then the slow carrier generation will never make much of a channel, as the charges will exit as quickly as they are generated; inversion won't happen, even though the surface potential would happily accommodate carriers there, and the voltage that you think of as producing a conductive channel won't do so.

These remarks are incorrect. You are imagining a transient situation where equilibrium demands a channel that has not formed. The situation to imagine instead is a steady-state with a channel maintained by communication with the source and drain, and the degree of occupancy available set by Vgb bending of the conduction band. I have added a diagram to show this situation. Brews ohare (talk) 17:22, 28 March 2012 (UTC)

"Can you then increase the conductivity by increasing the "voltage drop between the oxide-insulated gate electrode and its substrate" by lower the substrate to a negative voltage? No, you can't; that will increase Vth and turn the device more OFF. The idea the the "voltage drop between the oxide-insulated gate electrode and its substrate" is what makes the channel conduct fails, goes in the wrong direction"

Reverse biasing the source and drain does decrease the channel strength. That does not lead to your conclusion, however. For example, suppose that Vsb is present and Vgb is low. There is no channel. If now we increase Vgb at some point Vgb introduces a channel. The whole process is exactly the same as with Vsb=0, with the change that the Fermi level for occupancy of the conduction band is reduced by the Vsb of the source. So more Vgb is needed to bring the conduction band down close enough to the Fermi level set by the source, close enough for the conduction band to populate near the interface.

The mechanism of channel formation due to Vgb does not imply that increasing Vgb=Vgs+Vsb by reverse biasing the body and making Vsb >0 increases the channel strength. It means only what you said first, that Vsb increases the threshold voltage at which Vgb causes the channel to form. You have to bear in mind that a steady-state situation is in mind, not a transient one.

It seems as though you insist upon a pure electric field concept of Vgb, and insist upon ignoring the Vsb effect upon populating the channel effected by the change in Fermi level due to Vsb.

"Even at mid-channel, if the source voltage is too high, you'll get no channel, because all your mobile carriers will get away quickly. Right? In that sense, the stuff about channel formation and conductivity seems like just a conventional fiction, not very useful to understanding the current in any region other than strong inversion, and even that is determined more by the source than by the voltages that cause "inversion"."

You are introducing a non-equilibrium argument here by suggesting "quickly" has something to do with it. It doesn't. If Vsb reverse biases sufficiently, the channel is extinguished. The Fermi level is lowered. If now Vgb is increased sufficiently, the channel will reform. Carriers in the channel can move freely between source and channel in the final time-independent situation: the definition of Fermi level implies that the same work is done in removing a carrier from the channel as removing one from the source.

"I was never in the habit of paying attention to that conventional fiction, since I was working in weak inversion"

The description of MOSFET operation provided by text books applies to all operating regimes, including weak inversion. It won't do to describe this accepted analysis as a "conventional fiction". It is mathematically formulated and as accurate as knowledge of the doping distribution in the MOSFET allows. The concepts of strong and weak inversion and deep depletion all are introduced using the MOS capacitor, and they carry over to the MOSFET. The only change in the MOSFET is the ability to change the channel Fermi level using the source and drain contacts.

"In explaining the "field that adds carriers to the channel" you had to assume that the source is grounded. This is my point; it's Vgs that mostly matters, in terms of getting electrons into the channel."

That assumption is to provide a simple example. As pointed out above, Vgb creates the channel when Vsb is present, but it requires a large Vgb to bring the conduction band down to the Fermi level lowered by Vsb.

Dick, short of writing out the 1D Poisson equation with the Vsb Fermi-level effects in the minority carrier charge density and solving them, I don't see how any scheme of words will work. Of course, you may still insist that the equations, which are the same as the MOS capacitor equations, but with the added Vsb effect on Fermi level, are inapplicable, or a conventional fiction, or better described in terms of Vgs instead of Vgb. However one arrives at the 1D Poisson equation, it will prove difficult to explain how Vsb makes it into the 1D Poisson equation without introducing the idea of a change in Fermi level. Brews ohare (talk) 16:07, 28 March 2012 (UTC)

Brews, the equations are not at issue, applicability is. The equations assume an equilibrium in which electrons can collect into an inversion region. I'm just saying that that MOS-cap analysis is not compatible with what happens in a transistor when the source and drain are biased to remove those electrons as fast as they can be provided. You can still get an equilibrium of sorts, but the generation current will all be coming out the S/D terminals and the amount of inversion charge will be negligible, compared to the MOS-cap equilibrium. I'm just saying that therefore the MOS-cap analysis is a "convenient fiction" when applied to the transistor, in regions where it is inapplicable. It becomes more applicable when you discuss the effect of the field in forming a channel as forming a depleted region near the surface that can hold electrons, but then not assuming that those electrons will be there. That has generally been my attitude toward a "channel": it's a place that electrons can go through, even if the transistor is turned off due to a too-high source voltage, so there are not currently electrons in there. In this view, which is more like what we tend to use in subthreshold analysis, where the source boltzmann distribution relative to the channel barrier is key, the Vgb forms a "channel", but doesn't necessarily invert it, and doesn't directly affect "conductivity" in the channel, which is all about how many electrons actually get in there. As I have pointed out many times, and you haven't objected to, as far as I can see, moving the substrate in the direction that forms more a channel will tend to reduce conductivity, if the source and gate voltages are fixed, and that's why I say focusing on the gate-to-substrate voltage is misleading. None of the equations are wrong, but you can't understand channel conductivity by paying attention to Vgb and ignoring the source. Dicklyon (talk) 19:41, 28 March 2012 (UTC)

Dick you say:

" I'm just saying that that MOS-cap analysis is not compatible with what happens in a transistor when the source and drain are biased to remove those electrons as fast as they can be provided. You can still get an equilibrium of sorts, but the generation current will all be coming out the S/D terminals and the amount of inversion charge will be negligible, compared to the MOS-cap equilibrium."

I don't want to offend you, Dick, but this remark is rubbish. The inversion layer is determined as pointed out above, and is not based upon dynamics in which the SRH generation tries to compete with the drain and source sucking carriers out of the channel. The channel population is determined by the usual Boltzmann-Fermi statistics using the modified Fermi level for electrons. Please read over the texts I have suggested to you. Brews ohare (talk) 20:17, 28 March 2012 (UTC)

If I'm wrong I'll be happy to be set straight. You're saying that with positive voltages on the source and drain, the charges in the channel won't just diffuse over to and quickly exit to those terminals? Maybe that's true; I'll have to study up on the situation at the reverse baised junctions, which seem to me would have fields sucking away any electrons that diffuse over near them. And you still can't just talk about the "conductivity" between S and D, can you, if the current depends so much on the not just the Vds across the channel but also on where the source voltage sits relative to the gate and substrate? I guess I'm also concerned about the time scale. If it takes many seconds for thermally-generated carriers to collect to make an equilibrium (like with dark current in an image sensor), then the real operation of the device is going to be mostly determined by non-equilibrium conditions. Dicklyon (talk) 04:25, 29 March 2012 (UTC)

OK, I've reviewed the situation. Everything I see on MOSFETs supports my position that the channel inverts only when Vgs > VT. That is, no matter what you do with the voltage from gate to bulk, you need to have the gate high enough above the source to get electrons in the channel region. Are you saying that's not the case, or do we just misunderstand what we were arguing about? Dicklyon (talk) 05:28, 29 March 2012 (UTC)

Dick: You have not read my explanations in response to your various remarks. Nowhere have I suggested that inversion occurs regardless of the gate voltage. I have said several times and drafted a figure above to show that when Vsb reverse biases the source-to-substrate junction, the necessary gate voltage for inversion increases. The only way I can understand your remark above is that you have read none of these explanations. Nowhere have you addressed the Fermi level splitting caused by Vsb. You have simply slid past this fact. You again raise the issue of time scale, when what is being discussed is a steady-state, not a transient phenomenon. Brews ohare (talk) 14:32, 29 March 2012 (UTC)

And more

To the contrary. I have studied your explanation carefully. I did not mention any concept that is "regardless of the gate voltage". I'm talking about the effect of the source voltage, in cases where the gate and substrate are fixed to voltages that you say would cause an inversion layer. Why won't you acknowledge the question? The question is this: with gate and source high, and substrate low, where do the carriers go that are spontaneously generated? Do they collect along the oxide interface until you reach an equilibrium like the one in the MOS cap? Or do they diffuse to source and drain, and exit the transistor?

Brews, you've agreed that the MOSFET is a four-terminal device, but everything you say about it is as if the source were always low like the bulk; three-terminal thinking. Why can't you think about the case where the transistor is turned off by raising the source (and drain of course) to above Vg-VT? Is there a channel in this case or not? Is it inverted, or not? In my way of thinking, there's a channel, where electrons would be happy to be, but it's not inverted since any electrons that find themselves there are quickly swept out to S or D by the fields in the depletion regions around those n regions. In the "conventional fiction" based on only the MOS cap equilibrium, there would be electrons in the channel, and no distinction between channel and inversion. In a turned-off transistor with high-enough Vgb, these concepts have to be separated; but in most MOSFET descriptions, including everything you've ever written, they remain confused. Even in ones that are careful to get the channel charge right based on all the voltages, they don't specifically define channel and inversion separately, as fas as I can find, though some avoid inversion as the definition of channel and speak of a "channel region" instead. Alternatively, some speak of an "inversion layer" in a non-equilibrium sense as a place that collect electrons, which is how it is used in image sensors . Dicklyon (talk) 14:41, 29 March 2012 (UTC)

Dick, you say:

"everything you say about it is as if the source were always low like the bulk; three-terminal thinking. Why can't you think about the case where the transistor is turned off by raising the source (and drain of course) to above Vg-VT? Is there a channel in this case or not? Is it inverted, or not?"

My discussion covers every possible case. The voltages Vgb and Vsb both play a role. I have taken Vsd=0 for clarity; I don't think Vsd>0 makes any difference to the concepts. I have pointed out that Vsb>0 reverse biases the source-to-substrate junction and this lowers the Fermi level for populating the channel, and for large enough Vsb turns the channel off if Vgb is kept fixed. I believe that is repeated several times above and is the subject of the diagram provided.

I don't distinguish between an inversion layer and a channel. The inversion layer provides a conducting path from source to drain, which is the channel. Brews ohare (talk) 17:27, 29 March 2012 (UTC)

Nonequilibrium in the sense of transient behavior is not at issue here. Apart from the minor effects of the reverse current drawn through the reverse biased source-to-substrate junction, which makes this technically a steady-state problem, the situation is an equilibrium one, and the equation governing the situation is the standard MOS 1D Poisson equation along a line vertical to the gate extending through the substrate. The minority carrier density is altered by a factor related to Vsb due to the changed Fermi level. Can you address this picture directly? Brews ohare (talk) 17:17, 29 March 2012 (UTC)

OK, sorry, I can see that I was in error when I said that I had studied your explanation carefully. There are parts of it that I studied and disagreed with, and parts that are more OK. But fundamentally, there's still a problem region that the MOS cap approach is avoiding. Consider the nFET with 2 V threshold, with gate at 5 V, source and drain at 4 V, all relative to a grounded substrate. Is there charge in the channel, like there would be in a MOS cap with 5 V on it? No. If you move the S/D terminal up or down a volt (in the range of 3-5 V, so the transistor stays turned off and the junctions reverse biased), does it affect anything at mid channel? No, it just affects how much is depleted near those terminals. If you look at the current into the S+D, do you see the thermally generated current from the whole depletion region (or photocurrent if you shine a light on it), with only a little Vs voltage dependence from the changing depletion region size? Yes. Do we agree on that much at least? Do you want to call this steady state an equilibrium, or not? What do you call the mid-channel state in this case? Dicklyon (talk) 17:48, 29 March 2012 (UTC)

Compare a MOSFET with Vgb=5 Vt=2 Vsb=4 MOSFET to an MOS cap with Vgb=5 Vt=2. Is the same inversion layer present in both? Answer: No. Reason: Vsb lowers the Fermi level and depopulates the channel compared to the MOS capacitor. However, if one uses the MOS capacitor equation and adjusts the minority carrier density according to the Fermi level shift by Vsb, that modified 1D-Poisson analysis governs the MOSFET.

Does reverse bias when no channel is present affect midchannel? Answer: Practically speadking, no, but it depends upon what you are looking at. Reason: The situation of a long channel means the reverse bias depletes in a two-D pattern encircling the source. The electron Fermi level in the source and drain is dropped relative to the bulk. What is the Fermi level for the electrons at midchannel? Is it that of the source and drain, or that of the bulk material, or something in between? If the Fermi level for electrons varies with position, a current is drawn. Supposing the midchannel Fermi level is positioned somewhere between the bulk Fermi level and the source Fermi level, electrons will be drawn from midchannel toward the source. For a steady state to prevail a balance is achieved: electrons are drained to the source and supplied by SRH generation in the depletion region. The two balance in steady state, and a steady but extremely small current flows from bulk toward the source. For all practical purposes the slight gradient in Fermi level supporting this minute current toward the source is negligible and we can assume it is vanishingly small. That leads to the traditional approach, the assumption that the Fermi level for electrons across the entire device is set by the source and is flat.

Of course, if one were to do an experiment that actually measured the minute electron density at various positions, this approximation would introduce significant error in the electron density. But the electron charge in this situation is not important to device operation.

The 1D Poisson at midchannel with no electrons present leads to the same depletion depth as the MOS capacitor with the same gate voltage. That depth is not that of the source-to-body depletion region, of course, and is unaffected by the reverse bias on the source-to-body junction. As the gate bias is increased and the electron density becomes large enough to affect the 1D Poisson equation, the electron density is adequately represented by a Fermi level set by the source, because the miniscule current due to SRH generation still causes a negligible gradient in electron Fermi level. Brews ohare (talk) 18:53, 29 March 2012 (UTC)

OK, good, I understand you now, I think. You agree that the source voltage is crucial in determining whether a conductive channel forms, and that the mid-channel is affected by the source in a way that makes the turned-off transistor different from the MOS cap with same gate and bulk voltages in equilibrium. That takes me back to my original point that the statement in the lead is misleading. It says: "a voltage drop between the oxide-insulated gate electrode and its substrate induces a conducting channel between the source and drain contacts via the field effect." How can this make sense without the source voltage in the picture? I like how Sze and Ng do it better: "The source contact will be used as a voltage reference... When a sufficiently large positive bias is applied to the gate so that a surface inversion layer (or channel) is formed between the two n+ regions, the source and the drain are then connected through a conducting surface n-channel through which a large current can flow. The conductance of this channel can be modulated by varying the gate voltage. The back-surface contact (or substrate contact) can be at the reference voltage or reverse biased; this substrate voltage will also affect the channel conductance." It's not perfect, but not bad; with the source as reference, the source is playing a primary role; it is, after all, largely what determines the Fermi level that's relevant to channel formation, as you described, and plays a bigger role in modulating conductivity than the bulk does. That was my original point. That and the fact the statement we have would suggest a dependence on bulk voltage that goes the wrong direction is everything else is fixed (I realize this is not the intended or correct interpretation, which is why I say it's misleading). The other thing that's misleading about "a voltage drop between the oxide-insulated gate electrode and its substrate induces a conducting channel between the source and drain contacts via the field effect" and the way such statements and the MOS cap analysis often appear in sources is that they suggest that electrons are "drawn to" the channel, rather mysteriously, without saying where they come from. In the MOS cap, it can only be by thermal generation. But in the MOSFET, the affect of those generated carriers is negligible in all regions; when the source and drain are high, they get sucked out with negligible effect, as you describe, and as I kept trying to say without invoking Fermi; and in the ON state they're swamped by electrons from the source. So the MOS cap provides a good analogy, via the 1D Poisson equation and all, but not an explanation of how the transistor works, which is always much faster than the slow equilibrating of the MOS cap. Dicklyon (talk) 02:58, 30 March 2012 (UTC)

So I changed it to say "a voltage drop across the oxide induces a conducting channel between the source and drain contacts via the field effect." This "voltage drop across the oxide" seems to agree with all that you have been saying, and removes the part that I found misleading, by getting the substrate out of the picture, when the oxide field really just depends on the surface potential, which is affected by a combination of things. OK? Dicklyon (talk) 03:32, 30 March 2012 (UTC)

Dick I have no objection to the change to "oxide field". I don't agree with much else that you have said, but this form of words doesn't illuminate our differences, so it is fine.

A peculiarity of your description is the emphasis upon the source as having a "bigger role" when both the source and the gate have equally important roles to play. I don't share your view that MOS cap analysis has a mysterious aspect in drawing carriers into the channel, nor your description in the MOSFET of the source and drain sucking out carriers. The whole matter is subsumed by a simple statistical description of the equilibrium population of available energy levels by the Fermi function as set by the Fermi level. There is no need to draw carriers in or to suck them out. There is no dynamical aspect. Brews ohare (talk) 04:20, 30 March 2012 (UTC)

I'm saying the role of the source is greater than that of the bulk, not greater than that of the gate. And it's OK that you prefer the statistical view over looking at where the charge is moving. In the transistor, to me it seems that where it's moving is pretty important, and that's often made mysterious by focusing only on the statistical view. If you don't recognize that thermally generated charges are exiting at the source and drain rather than collecting under the oxide when the source voltage is high, then it's harder to understand where they are or where they go. You did finally convince me by talking about that that it's not inconsistent with the statistical view, as long as you modify the MOS cap analysis to have a different surface potential set by the source. Dicklyon (talk) 05:35, 30 March 2012 (UTC)

OK, Dick. Just to nit pick a bit, it is voltage differences that control the device, so it is Vgb, and Vsb. (i'm taking Vds=0 for the moment.) When Vsb=0, Vgb can form a channel. When Vgb=0, Vsb cannot form a channel. So one might argue over which is more "important". IMO the easiest perspective is that Vgb positions the energy levels (the conduction band) while Vsb positions the Fermi level deciding occupancy of these levels. What do you thinki about that? Brews ohare (talk) 15:46, 30 March 2012 (UTC)

I added a sentence to the body-effect section like this. Brews ohare (talk) 17:14, 30 March 2012 (UTC)

Yes, that sounds like a clear way to put it. Dicklyon (talk) 17:40, 30 March 2012 (UTC)

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