Apple A7: Difference between revisions

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	== Design ==		== Design ==
	The A7 features an Apple-designed<ref name="AnandTech-iPhone5s-A7" /> 64-bit<ref name="AnandTech-iPhone5s-64-bit">{{cite web \|first=Anand \|last=Lal Shimpi \|url=http://anandtech.com/show/7335/the-iphone-5s-review/4 \|title=The iPhone 5s Review: The Move to 64-bit \|date= September 17, 2013 \|publisher=AnandTech \|accessdate= September 18, 2013}}</ref> 1.3 GHz<ref name="AnandTech-iPhone5s-A7">{{cite web \|first=Anand \|last=Lal Shimpi \|url=http://anandtech.com/show/7335/the-iphone-5s-review/2 \|title=The iPhone 5s Review: A7 SoC Explained \|publisher=AnandTech \|date= September 17, 2013 \|accessdate= September 18, 2013}}</ref> ]<ref name="AnandTech-iPhone5s-Cyclone">{{cite web \|first=Anand \|last=Lal Shimpi \|url=http://anandtech.com/show/7335/the-iphone-5s-review/3 \|title=The iPhone 5s Review: After Swift Comes Cyclone \|date= September 17, 2013\|publisher=AnandTech \|accessdate= September 18, 2013}}</ref><ref name="LLVM-5s-ARMv8">{{cite web\|url=http://lists.cs.uiuc.edu/pipermail/llvmdev/2013-September/065480.html \|title=],<ref name="AnandTech-iPhone5s-A7" /> called Cyclone,<ref name="AnandTech-iPhone5s-Cyclone" /> and an integrated ] ] (GPU) in a four cluster configuration.<ref name="AnandTech-iPhone5s-GPU">{{cite web \|first=Anand \|last=Lal Shimpi \|url=http://anandtech.com/show/7335/the-iphone-5s-review/7 \|title=The iPhone 5s Review: GPU Architecture \|date= September 17, 2013 \|publisher=AnandTech \|accessdate= September 18, 2013}}</ref> The ARMv8 microarchitecture doubles the number of ] of the A7 compared to the A6.<ref name="Ars: Apple unveils">{{cite web \|last=Cunningham \|first=Andrew \|url= http://arstechnica.com/apple/2013/09/apple-unveils-64-bit-iphone-5s/ \|title=Apple unveils 64-bit iPhone 5S with fingerprint scanner, $199 for 16GB \|publisher=Ars Technica \|date=2013-09-10 \|accessdate=2013-09-12}}</ref> It now has 31 general purpose registers that are each 64-bits wide and 32 floating-point/] registers that are each 128-bits wide.<ref name="AnandTech-iPhone5s-64-bit" /> It has a per-core ] of 64 KB for data and 64 KB for instructions and a shared L2 cache of 1 MB.<ref name="AnandTech-iPhone5s-Cyclone" /> The A7 processor package also incorporates 1 GB of ] DRAM<ref name="TechInsights-iPhone5s">{{cite web \|url= http://www.techinsights.com/apple-iphone-5s/ \|title= Quick Turn Teardown of the Apple iPhone 5s \|publisher=TechInsights \|date=September 20, 2013 \|accessdate=September 20, 2013}}</ref> with a 64-bit wide memory interface.<ref name="AnandTech-iPhone5s-Cyclone" />		The A7 features an Apple-designed<ref name="AnandTech-iPhone5s-A7" /> 64-bit<ref name="AnandTech-iPhone5s-64-bit">{{cite web \|first=Anand \|last=Lal Shimpi \|url=http://anandtech.com/show/7335/the-iphone-5s-review/4 \|title=The iPhone 5s Review: The Move to 64-bit \|date= September 17, 2013 \|publisher=AnandTech \|accessdate= September 18, 2013}}</ref> 1.3 GHz<ref name="AnandTech-iPhone5s-A7">{{cite web \|first=Anand \|last=Lal Shimpi \|url=http://anandtech.com/show/7335/the-iphone-5s-review/2 \|title=The iPhone 5s Review: A7 SoC Explained \|publisher=AnandTech \|date= September 17, 2013 \|accessdate= September 18, 2013}}</ref> ]<ref name="AnandTech-iPhone5s-Cyclone">{{cite web \|first=Anand \|last=Lal Shimpi \|url=http://anandtech.com/show/7335/the-iphone-5s-review/3 \|title=The iPhone 5s Review: After Swift Comes Cyclone \|date= September 17, 2013\|publisher=AnandTech \|accessdate= September 18, 2013}}</ref><ref name="LLVM-5s-ARMv8">{{cite web\|url=http://lists.cs.uiuc.edu/pipermail/llvmdev/2013-September/065480.html \|title=],<ref name="AnandTech-iPhone5s-A7" /> called Cyclone,<ref name="AnandTech-iPhone5s-Cyclone" /> and an integrated ] ] (GPU) in a four cluster configuration.<ref name="AnandTech-iPhone5s-GPU">{{cite web \|first=Anand \|last=Lal Shimpi \|url=http://anandtech.com/show/7335/the-iphone-5s-review/7 \|title=The iPhone 5s Review: GPU Architecture \|date= September 17, 2013 \|publisher=AnandTech \|accessdate= September 18, 2013}}</ref> The ARMv8 microarchitecture doubles the number of ] of the A7 compared to the A6.<ref name="Ars: Apple unveils">{{cite web \|last=Cunningham \|first=Andrew \|url= http://arstechnica.com/apple/2013/09/apple-unveils-64-bit-iphone-5s/ \|title=Apple unveils 64-bit iPhone 5S with fingerprint scanner, $199 for 16GB \|publisher=Ars Technica \|date=2013-09-10 \|accessdate=2013-09-12}}</ref> It now has 31 general purpose registers that are each 64-bits wide and 32 floating-point/] registers that are each 128-bits wide.<ref name="AnandTech-iPhone5s-64-bit" /> It has a per-core ] of 64 ] for data and 64 KB for instructions and a shared L2 cache of 1 ].<ref name="AnandTech-iPhone5s-Cyclone" /> The A7 processor package also incorporates 1 GB of ] DRAM<ref name="TechInsights-iPhone5s">{{cite web \|url= http://www.techinsights.com/apple-iphone-5s/ \|title= Quick Turn Teardown of the Apple iPhone 5s \|publisher=TechInsights \|date=September 20, 2013 \|accessdate=September 20, 2013}}</ref> with a 64-bit wide memory interface.<ref name="AnandTech-iPhone5s-Cyclone" />

	The A7 includes a new ] (ISP), a feature originally introduced in the ], used for functionality related to the camera such as image stabilizing, color correction and light balance.<ref>{{cite web \|url=http://www.apple.com/iphone-5s/design/ \|title=iPhone 5s - Design \|publisher=] \|date=2013-09-10 \|accessdate=2013-09-13}}</ref><ref>{{cite web \|last=Panzarino \|first=Matthew \|url= http://techcrunch.com/2013/09/12/a-photographers-take-on-the-iphone-5s-camera/ \|title=A Photographer’s Take On The iPhone 5S Camera \|publisher=TechCrunch \|date=2013-09-12 \|accessdate=2013-09-13}}</ref> The A7 also includes an area called the ''Secure Enclave'' that stores and protects the data from the iPhone 5s' ] fingerprint sensor.<ref name="Apple iPhone 5s PR" /> The Secure Enclave implements ARM's ]/] technology to keep sensitive data secure.<ref></ref>{{dubious\|Secure Enclave via TrustZone/SecureCore\|date=September 2013}} In a change from the ], the A7 SoC no longer services the accelerometer, gyroscope and compass. In order to reduce power consumption, this functionality has been moved to the new ] motion ] <ref name="AnandTech-iPhone5s-M7">{{cite web \|first=Anand \|last=Lal Shimpi \|url=http://anandtech.com/show/7335/the-iphone-5s-review/8 \|title=The iPhone 5s Review: M7 Motion Coprocessor \|publisher=AnandTech \|date= September 17, 2013 \|accessdate= September 18, 2013}}</ref><ref>{{cite web\|last=Lawler \|first=Richard \|url=http://www.engadget.com/2013/09/10/iphone-5s-m7-coremotion-motion-coprocessor/ \|title=iPhone 5s packs M7 motion-sensing chip, CoreMotion API for more accurate tracking \|publisher=Engadget \|date=2013-09-10 \|accessdate=2013-09-11}}</ref> which appears to be a separate ARM-based microcontroller from ].<ref name="Chipworks-iPhone5s">{{cite web\|url=http://www.chipworks.com/en/technical-competitive-analysis/resources/blog/inside-the-iphone-5s/\|title=Inside the iPhone 5s\|first1=Jason\|last1=Tanner\|first2=Jim\|last2=Morrison\|first3=Dick\|last3=James\|first4=Ray\|last4=Fontaine\|first5=Phil\|last5=Gamache\|publisher=Chipworks\|date=September 20, 2013\|accessdate=September 20, 2013}}</ref>		The A7 includes a new ] (ISP), a feature originally introduced in the ], used for functionality related to the camera such as image stabilizing, color correction and light balance.<ref>{{cite web \|url=http://www.apple.com/iphone-5s/design/ \|title=iPhone 5s - Design \|publisher=] \|date=2013-09-10 \|accessdate=2013-09-13}}</ref><ref>{{cite web \|last=Panzarino \|first=Matthew \|url= http://techcrunch.com/2013/09/12/a-photographers-take-on-the-iphone-5s-camera/ \|title=A Photographer’s Take On The iPhone 5S Camera \|publisher=TechCrunch \|date=2013-09-12 \|accessdate=2013-09-13}}</ref> The A7 also includes an area called the ''Secure Enclave'' that stores and protects the data from the iPhone 5s' ] fingerprint sensor.<ref name="Apple iPhone 5s PR" /> The Secure Enclave implements ARM's ]/] technology to keep sensitive data secure.<ref></ref>{{dubious\|Secure Enclave via TrustZone/SecureCore\|date=September 2013}} In a change from the ], the A7 SoC no longer services the accelerometer, gyroscope and compass. In order to reduce power consumption, this functionality has been moved to the new ] motion ] <ref name="AnandTech-iPhone5s-M7">{{cite web \|first=Anand \|last=Lal Shimpi \|url=http://anandtech.com/show/7335/the-iphone-5s-review/8 \|title=The iPhone 5s Review: M7 Motion Coprocessor \|publisher=AnandTech \|date= September 17, 2013 \|accessdate= September 18, 2013}}</ref><ref>{{cite web\|last=Lawler \|first=Richard \|url=http://www.engadget.com/2013/09/10/iphone-5s-m7-coremotion-motion-coprocessor/ \|title=iPhone 5s packs M7 motion-sensing chip, CoreMotion API for more accurate tracking \|publisher=Engadget \|date=2013-09-10 \|accessdate=2013-09-11}}</ref> which appears to be a separate ARM-based microcontroller from ].<ref name="Chipworks-iPhone5s">{{cite web\|url=http://www.chipworks.com/en/technical-competitive-analysis/resources/blog/inside-the-iphone-5s/\|title=Inside the iPhone 5s\|first1=Jason\|last1=Tanner\|first2=Jim\|last2=Morrison\|first3=Dick\|last3=James\|first4=Ray\|last4=Fontaine\|first5=Phil\|last5=Gamache\|publisher=Chipworks\|date=September 20, 2013\|accessdate=September 20, 2013}}</ref>

Revision as of 18:32, 22 September 2013

Apple A7
General information
The A7 processor
Launched	September 20, 2013
Discontinued	Present
Designed by	Apple Inc.
Common manufacturer	Samsung
Product code	S5L8960X
Performance
Max. CPU clock rate	1.3 GHz
Cache
L1 cache	64 KB instruction + 64 KB data
L2 cache	1 MB shared
Architecture and classification
Application	Mobile
Technology node	28 nm
Microarchitecture	Cyclone
Instruction set	ARMv8
Physical specifications
Cores	2
GPU	PowerVR G6430 (four cluster)
History
Predecessor	Apple A6

The Apple A7 is a package on package (PoP) 64-bit system on a chip (SoC) designed by Apple Inc. It first appeared in the iPhone 5S, which was introduced on September 10, 2013. Apple states that it is up to twice as fast and has up to twice the graphics power compared to its predecessor the Apple A6. While not the first 64-bit ARM CPU, AnandTech makes the claim that the A7 chipset "is the world's first consumer ARM based with 64-bit support."

Design

The A7 features an Apple-designed 64-bit 1.3 GHz ARMv8 dual-core CPU, called Cyclone, and an integrated PowerVR G6430 graphics processing unit (GPU) in a four cluster configuration. The ARMv8 microarchitecture doubles the number of registers of the A7 compared to the A6. It now has 31 general purpose registers that are each 64-bits wide and 32 floating-point/NEON registers that are each 128-bits wide. It has a per-core L1 cache of 64 KB for data and 64 KB for instructions and a shared L2 cache of 1 MB. The A7 processor package also incorporates 1 GB of LPDDR3 DRAM with a 64-bit wide memory interface.

The A7 includes a new image signal processor (ISP), a feature originally introduced in the A5, used for functionality related to the camera such as image stabilizing, color correction and light balance. The A7 also includes an area called the Secure Enclave that stores and protects the data from the iPhone 5s' Touch ID fingerprint sensor. The Secure Enclave implements ARM's TrustZone/SecureCore technology to keep sensitive data secure. In a change from the Apple A6, the A7 SoC no longer services the accelerometer, gyroscope and compass. In order to reduce power consumption, this functionality has been moved to the new Apple M7 motion coprocessor which appears to be a separate ARM-based microcontroller from NXP Semiconductors.

The A7 is manufactured by Samsung on a high-κ metal gate (HKMG) 28 nm process and the chip includes over 1 billion transistors on a die 102 mm in size.

Products that include the Apple A7

iPhone 5S

References

^ Tanner, Jason; Morrison, Jim; James, Dick; Fontaine, Ray; Gamache, Phil (September 20, 2013). "Inside the iPhone 5s". Chipworks. Retrieved September 20, 2013.
Gurman, Mark (2013-07-31). "Apple's upcoming A7 iPhone chip will have Samsung components, code inside iOS 7 reveals". 9to5Mac. Retrieved 2013-09-13.
^ Lal Shimpi, Anand (September 17, 2013). "The iPhone 5s Review: A7 SoC Explained". AnandTech. Retrieved September 18, 2013.
^ Lal Shimpi, Anand (September 17, 2013). "The iPhone 5s Review: After Swift Comes Cyclone". AnandTech. Retrieved September 18, 2013.
^ Lal Shimpi, Anand (September 17, 2013). "The iPhone 5s Review: The Move to 64-bit". AnandTech. Retrieved September 18, 2013.
^ "[LLVMdev] A7 processor support?". LLVM Developers Mailing List. 2013-09-10. Retrieved 2013-09-11.
^ Lal Shimpi, Anand (September 17, 2013). "The iPhone 5s Review: GPU Architecture". AnandTech. Retrieved September 18, 2013.
^ "Apple Announces iPhone 5s—The Most Forward-Thinking Smartphone in the World". Apple. 2013-09-10. Retrieved 2013-09-13.
"AppliedMicro Showcases World's First 64-bit ARM v8 Core". AppliedMicro. October 27, 2011. Retrieved September 18, 2013.
Lai Shimpi, Anand (September 10, 2013). "Apple Announces A7, World's First 64-bit Smartphone SoC". AnandTech. Retrieved September 16, 2013.
Cunningham, Andrew (2013-09-10). "Apple unveils 64-bit iPhone 5S with fingerprint scanner, $199 for 16GB". Ars Technica. Retrieved 2013-09-12.
"Quick Turn Teardown of the Apple iPhone 5s". TechInsights. September 20, 2013. Retrieved September 20, 2013.
"iPhone 5s - Design". Apple. 2013-09-10. Retrieved 2013-09-13.
Panzarino, Matthew (2013-09-12). "A Photographer's Take On The iPhone 5S Camera". TechCrunch. Retrieved 2013-09-13.
What is Apple’s new Secure Enclave and why is it important?
Lal Shimpi, Anand (September 17, 2013). "The iPhone 5s Review: M7 Motion Coprocessor". AnandTech. Retrieved September 18, 2013.
Lawler, Richard (2013-09-10). "iPhone 5s packs M7 motion-sensing chip, CoreMotion API for more accurate tracking". Engadget. Retrieved 2013-09-11.
AnandTech | Chipworks Confirms Apple's A7 is Built On Samsung's 28nm HK+MG Process

iOS and iOS-based products

Hardware

iPhone	1st 3G 3GS 4 4s 5 5c 5s 6 & 6 Plus 6s & 6s Plus 7 & 7 Plus 8 & 8 Plus X XR XS & XS Max 11 11 Pro & Pro Max 12 & 12 Mini 12 Pro & Pro Max 13 & 13 Mini 13 Pro & Pro Max 14 & 14 Plus 14 Pro & Pro Max 15 & 15 Plus 15 Pro & Pro Max 16 & 16 Plus 16 Pro & Pro Max SE 1st 2nd 3rd
iPod Touch	1st 2nd 3rd 4th 5th 6th 7th
iPad	1st 2 3rd 4th 5th 6th 7th 8th 9th 10th Mini 1st 2 3 4 5th 6th 7th Air 1st 2 3rd 4th 5th 6th Pro 1st 2nd 3rd 4th 5th 6th 7th
Other	Apple TV Apple Watch HomePod Mini

Software

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
Derived from iOS	watchOS tvOS iPadOS 13 14 15 16 17 18

Features

SDK & API

Bundled apps

Books Calculator Calendar Clock Contacts FaceTime Freeform Files Find My Fitness Workouts Health Mindfulness Home Journal Mail Maps Measure Messages Music News Notes Passwords Photos Podcasts Reminders Safari Shortcuts Stocks Translate TV Voice Memos Wallet Weather Watch
Discontinued	Find My Friends Find My iPhone Newsstand

Apple apps

Classroom Clips GarageBand iMovie iWork Keynote Numbers Pages
Discontinued	Beats Music iPhoto Nike+iPod iTunes Remote

Services

Arcade Card App Store Music FaceTime Family Sharing Game Center iCloud iMessage iTunes Connect iTunes Store News + One Pay Push Notifications TestFlight TV+ Shows Wallet
Discontinued	iAd iLife iTunes Radio MobileMe

Other

Category

ARM-based chips

Application ARM-based chips

Application
processors
(32-bit)

ARMv7-A

Cortex-A5	Actions ATM702x Amlogic M805/S805, T82x Atmel SAMA5D3 InfoTM iMAPx820, iMAPx15 Qualcomm Snapdragon S4 Play, 200 RDA RDA8810PL Telechips TCC892x
Cortex-A7	Allwinner A2x, A3x, A83T, H3, H8 NXP i.MX7, QorIQ LS10xx, NXP i.MX6UL Broadcom VideoCore BCM2836, BCM23550 Leadcore LC1813, LC1860/C, LC1913, LC1960 Marvell Armada PXA1920, 1500 mini plus MediaTek MT65xx Qualcomm Snapdragon 200, 205, 208, 210, 212, 400
Cortex-A8	Allwinner A1x Apple A4 Freescale i.MX5 Rockchip RK291x Samsung Exynos 3110(S5PC110), S5PV210 Texas Instruments OMAP 3 Texas Instruments Sitara AM3xxx Texas Instruments DM38x ZiiLABS ZMS-08
Cortex-A9	Actions ATM702x, ATM703x Altera Cyclone V, Arria V/10 Amlogic AML8726, MX, M6x, M801, M802/S802, S812, T86x Apple A5, A5X Broadcom VideoCore BCM21xxx, BCM28xxx Freescale i.MX6 HiSilicon K3V2, 910's InfoTM iMAPx912 Leadcore LC1810, LC1811 Marvell Armada 1500 mini MediaTek MT65xx Nvidia Tegra, 2, 3, 4i Nufront NuSmart 2816M, NS115, NS115M Renesas EMMA EV2, R-Car H1, RZ/A Rockchip RK292x, RK30xx, RK31xx Samsung Exynos 4 421x, 441x ST-Ericsson NovaThor Telechips TCC8803 Texas Instruments OMAP 4 Texas Instruments Sitara AM4xxx VIA WonderMedia WM88x0, 89x0 Xilinx Zynq-7000 ZiiLABS ZMS-20, ZMS-40
Cortex-A15	Allwinner A80 HiSilicon K3V3 MediaTek MT8135/V Nvidia Tegra 4, K1 Renesas R-Car H2 Samsung Exynos 5 52xx, 54xx Texas Instruments OMAP 5, DRA7xx, AM57xx Texas Instruments Sitara AM5xxx
Cortex-A17	MediaTek MT6595, MT5595 MStar 6A928 Rockchip RK3288
Others	Cortex-A12
ARMv7-A compatible	Apple A6, A6X, S1, S1P, S2, S3 Broadcom Brahma-B15 Marvell P4J Qualcomm Snapdragon S1, S2, S3, S4 Plus, S4 Pro, 600, 800 (Scorpion, Krait)

ARMv8-A

Others	Cortex-A32

Application
processors
(64-bit)

ARMv8-A

Cortex-A35	NXP i.MX8X MediaTek MT6799, MT8516 Rockchip RK3308
Cortex-A53	Actions GT7, S900, V700 Allwinner A64, H5, H64, R18 Altera Stratix 10 Amlogic S9 Family, T96x Broadcom BCM2837 EZchip TILE-Mx100 HiSilicon Kirin 620, 650, 655, 658, 659, 930, 935 Marvell Armada PXA1928, Mobile PXA1908/PXA1936 MediaTek MT673x, MT675x, MT6761V, MT6762/V, MT6763T, MT6765/G/H, MT6795, MT8161, MT8163, MT8165, MT8732, MT8735, MT8752 NXP ARM S32, QorIQ LS1088, LS1043, i.MX8M Qualcomm Snapdragon 215, 410, 412, 415, 425, 427, 429, 430, 435, 439, 450, 610, 615, 616, 617, 625, 626, 630 Renesas RZ/V2M Rockchip RK3328, RK3368 Samsung Exynos 7570, 7578, 7580, 7870, 7880 Texas Instruments Sitara AM6xxx UNISOC SC9820E, SC9832E, SC9860/GV Xilinx ZynqMP
Cortex-A57	AMD Opteron A1100-series NXP QorIQ LS20xx Nvidia Tegra X1 and Tegra X2 Qualcomm Snapdragon 808 and 810 Samsung Exynos 7 5433, 7420 HiSilicon Kirin Hi1610 and Hi1612
Cortex-A72	AWS Graviton Broadcom BCM2711 HiSilicon Kirin 950, 955, Kunpeng 916 MediaTek MT6797/D/T/X, MT8173, MT8176, MT8693 MStar 6A938 Qualcomm Snapdragon 650, 652, 653 Rockchip RK3399 NXP QorIQ LS2088, QorIQ LS1046A, QorIQ LX2160A, QorIQ LS1028A, i.MX8
Cortex-A73	Qualcomm Snapdragon 460, 632, 636, 660, 662, 665, 680, 685, 6s 4G Gen 1, 835 Samsung Exynos 7872, 7884, 7885, 7904, 9609, 9610, 9611 HiSilicon Kirin 710, 960, 970 MediaTek MT6771/V, MT6799, MT8183, MT8788 Amlogic S922X
Others	Cortex-A34
ARMv8-A compatible	Ampere eMAG Apple A7, A8, A8X, A9, A9X, A10, A10X Applied Micro X-Gene Cavium ThunderX Nvidia Tegra K1 (Denver), Tegra X2 (Denver2) Qualcomm Kryo, Falkor Samsung Exynos M1 (Mongoose), M2 (Mongoose)

ARMv8.1-A

ARMv8.1-A compatible	Cavium ThunderX2

ARMv8.2-A

Cortex-A55	Allwinner A523 Samsung Exynos 850 UNISOC SC9863/A, T603
Cortex-A75	Qualcomm Snapdragon 670, 710, 712, 845, 850 Samsung Exynos 9820, 9825 MediaTek MT6769H/T/V/Z, MT6768, MT6779V UNISOC T310, T606, T610, T615, T616, T618, T619, T620, T700, T710, T7200, T7225, T7250, T7255, T7280, T740
Cortex-A76	Allwinner A733 Google Tensor HiSilicon Kirin 810, 820, 980, 985, 990 Qualcomm Snapdragon 480(+), 675, 678, 720G, 730(G), 732G, 765(G), 768G, 855(+), 860, 7c (Gen 2), 8c, 8cx (Gen 2) Microsoft SQ1 and SQ2 MediaTek MT6781, MT6785V, MT6789, MT6833V/P, MT6853V/T, MT6873, MT6875, Dimensity 6020, 6080, 6100+, 6300(+), MT8192 Samsung Exynos 990 UNISOC T750, T760, T765, T770, T820, T8100, T8200, T9100
Cortex-A77	MediaTek Dimensity 1000(+) Qualcomm Snapdragon 690, 750G, 865(+), 870 HiSilicon Kirin 9000 Samsung Exynos 880, 980
Cortex-A78	Google Tensor G2 MediaTek MT6877, MT6878, MT6879, MT6891, MT6893, Dimensity 7020, 7025(Ultra), 7030, 7050, 7300(Energy/X), 8000, 8020, 8050, 8100, 8200, Kompanio 900T, 1200, 1380, 1300T Qualcomm Snapdragon 4 Gen 1, 4(s) Gen 2, 695, 6 Gen 1, 6(s) Gen 3, 778G(+), 780G, 782G, 888(+) Samsung Exynos 1080, 1280, 1330, 1380, 2100
Cortex-X1	Google Tensor, Tensor G2 Qualcomm Snapdragon 888(+) Samsung Exynos 2100
Neoverse N1	Ampere Altra, Altra Max AWS Graviton2
Others	Cortex-A65, Cortex-A65AE, Cortex-A76AE, Cortex-A78C, Cortex-X1C, Neoverse E1
ARMv8.2-A compatible	Apple A11 Fujitsu A64FX HiSilicon TaiShan v110 Nvidia Tegra Xavier (Carmel) Samsung Exynos M3 (Meerkat), M4 (Cheetah), M5 (Lion)

ARMv8.3-A

ARMv8.3-A compatible	Apple A12, A12X/A12Z, S4, S5 Marvell ThunderX3

ARMv8.4-A

Neoverse V1	AWS Graviton3
ARMv8.4-A compatible	Apple A13, S6, S7, S8

ARMv8.5-A

ARMv8.5-A compatible	Apple A14, M1

ARMv8.6-A

ARMv8.6-A compatible	Apple A15, A16, A17, M2, M3

ARMv8.7-A

ARMv8.7-A compatible	Qualcomm Oryon

ARMv9.0-A

Cortex-A510	Google Tensor G3 MediaTek Dimensity 7200 (Pro/Ultra), 8300 (Ultra), 9000/9000+, 9200 Qualcomm Snapdragon 7 Gen 1, 7 Gen 3, 7s/7+ Gen 2, 8(+) Gen 1, 8 Gen 2 Samsung Exynos 2200
Cortex-A710	MediaTek Dimensity 9000/9000+ Qualcomm Snapdragon 7 Gen 1, 7 Gen 3, 7s/7+ Gen 2, 8(+) Gen 1, 8 Gen 2 Samsung Exynos 2200
Cortex-A715	Google Tensor G3 MediaTek Dimensity 7200 (Pro/Ultra), 8300 (Ultra), 9200 Qualcomm Snapdragon 7 Gen 3, 8 Gen 2
Cortex-X2	MediaTek Dimensity 9000/9000+ Qualcomm Snapdragon 7s/7+ Gen 2, 8(+) Gen 1 Samsung Exynos 2200
Cortex-X3	Google Tensor G3 MediaTek Dimensity 9200/9200+ Qualcomm Snapdragon 8 Gen 2
Neoverse N2	Alibaba YiTian 710 Microsoft Azure Cobalt 100
Neoverse V2	AWS Graviton4 Google Axion Nvidia Grace

ARMv9.2-A

Cortex-A520	Google Tensor G4 Qualcomm Snapdragon 7s/7+ Gen 3, Snapdragon 8(s) Gen 3 Samsung Exynos 2400
Cortex-A720	Google Tensor G4 MediaTek Dimensity 9300(+) Qualcomm Snapdragon 7s/7+ Gen 3, Snapdragon 8(s) Gen 3 Samsung Exynos 2400
Cortex-X4	Google Tensor G4 MediaTek Dimensity 9300(+) Qualcomm Snapdragon 7+ Gen 3, Snapdragon 8(s) Gen 3 Samsung Exynos 2400
Cortex-X925	MediaTek Dimensity 9400(+)
Neoverse N3	-
Neoverse V3	-
ARMv9.2-A compatible	Apple A18 Apple M4

Embedded ARM-based chips

Embedded
microcontrollers

Cortex-M0	Cypress PSoC 4000, 4100, 4100M, 4200, 4200DS, 4200L, 4200M Infineon XMC1000 Nordic nRF51 NXP LPC1100, LPC1200 nuvoTon NuMicro Sonix SN32F700 STMicroelectronics STM32 F0 Toshiba TX00 Vorago VA108x0
Cortex-M0+	Cypress PSoC 4000S, 4100S, 4100S+, 4100PS, 4700S, FM0+ Holtek HT32F52000 Microchip (Atmel) SAM C2, D0, D1, D2, DA, L2, R2, R3 NXP LPC800, LPC11E60, LPC11U60 NXP (Freescale) Kinetis E, EA, L, M, V1, W0 Raspberry Pi RP2040 Renesas Synergy S1 Silicon Labs (Energy Micro) EFM32 Zero, Happy STMicroelectronics STM32 L0
Cortex-M1	Altera FPGAs Cyclone-II, Cyclone-III, Stratix-II, Stratix-III Microsemi (Actel) FPGAs Fusion, IGLOO/e, ProASIC3L, ProASIC3/E Xilinx FPGAs Spartan-3, Virtex-2-3-4
Cortex-M3	Actel SmartFusion, SmartFusion 2 Analog Devices ADuCM300 Cypress PSoC 5000, 5000LP, FM3 Fujitsu FM3 Holtek HT32F Microchip (Atmel) SAM 3A, 3N, 3S, 3U, 3X NXP LPC1300, LPC1700, LPC1800 ON Semiconductor Q32M210 Silicon Labs Precision32 Silicon Labs (Energy Micro) EFM32 Tiny, Gecko, Leopard, Giant STMicroelectronics STM32 F1, F2, L1 Texas Instruments F28, LM3, TMS470, OMAP 4 Toshiba TX03
Cortex-M4	Microchip (Atmel) SAM 4L, 4N, 4S NXP (Freescale) Kinetis K, W2 Renesas RA4W1, RA6M1, RA6M2, RA6M3, RA6T1
Cortex-M4F	Cypress 6200, FM4 Infineon XMC4000 Microchip (Atmel) SAM 4C, 4E, D5, E5, G5 Microchip CEC1302 Nordic nRF52 NXP LPC4000, LPC4300 NXP (Freescale) Kinetis K, V3, V4 Renesas Synergy S3, S5, S7 Silicon Labs (Energy Micro) EFM32 Wonder STMicroelectronics STM32 F3, F4, L4, L4+, WB Texas Instruments LM4F/TM4C, MSP432 Toshiba TX04
Cortex-M7F	Microchip (Atmel) SAM E7, S7, V7 NXP (Freescale) Kinetis KV5x, i.MX RT 10xx, i.MX RT 11xx, S32K3xx STMicroelectronics STM32 F7, H7
Cortex-M23	GigaDevice CD32E2xx Microchip (Atmel) SAM L10, L11, and PIC 32CM-LE 32CM-LS Nuvoton M23xx family, M2xx family, NUC1262, M2L31 Renesas S1JA, RA2A1, RA2L1, RA2E1, RA2E2
Cortex-M33F	Analog Devices ADUCM4 Dialog DA1469x GigaDevice GD32E5, GD32W5 Nordic nRF91, nRF5340, nRF54 NXP LPC5500, i.MX RT600 ON RSL15 Renesas RA4, RA6 ST STM32 H5, L5, U5, WBA Silicon Labs Wireless Gecko Series 2
Cortex-M35P	STMicroelectronics ST33K
Cortex-M55F	Alif Semiconductor Ensemble Infineon PSoC Edge
Cortex-M85F	Renesas RA8

Real-time
microprocessors

Cortex-R4F	Texas Instruments RM4, TMS570 Renesas RZ/T1
Cortex-R5F	Scaleo OLEA Texas Instruments RM57, AM2 Xilinx Versal, ZynqMP, ZynqRF
Cortex-R7F	Renesas RZ/G2E, RZ/G2H, RZ/G2M, RZ/G2N
Cortex-R52F	NXP S32Z, S32E Renesas RZ/N2L, RZ/T2L, RZ/T2M
Cortex-R52+F	STMicroelectronics Stellar G, Stellar P

Classic ARM-based chips

Classic
processors

ARM7	Atmel SAM7L, SAM7S, SAM7SE, SAM7X, SAM7XC, AT91CAP7, AT91M, AT91R Cirrus Logic PS7xxx, EP7xxx Mediatek MT62xx NXP LPC2100, LPC2200, LPC2300, LPC2400, LH7 STMicroelectronics STR7
ARM9	Aspeed AST2400 Atmel SAM9G, SAM9M, SAM9N, SAM9R, SAM9X, SAM9XE, SAM926x, AT91CAP9 Cirrus Logic EP9xxx Freescale i.MX1x, i.MX2x Nuvoton NUC900 NXP LPC2900, LPC3000, LH7A Philips Nexperia PNX4008 Rockchip RK27xx, RK28xx Samsung S3C24xx STMicroelectronics Nomadik STn881x STMicroelectronics STR9 Texas Instruments OMAP 1, AM1x, DaVinci VIA WonderMedia WM8505/8650 ZiiLABS ZMS-05
ARM11	Broadcom BCM2835 Cavium CNS3xxx Freescale i.MX3x Infotmic IMAPX210/220 Mindspeed Comcerto 1000 Nvidia Tegra APX, 6xx Qualcomm MSM7000, Snapdragon S1 Samsung S3C64xx, S5P64xx ST-NXP Wireless Nomadik STn882x Telechips TCC8902 Texas Instruments OMAP 2 VIA WonderMedia WM87x0
ARMv2a compatible	Amber (open FPGA core)
ARMv4 compatible	Faraday FA526, FA626 DEC/Intel StrongARM
ARMv5TE compatible	Intel/Marvell XScale Marvell Sheeva, Feroceon, Jolteon, Mohawk Faraday FA606TE, FA616TE, FA626TE, FA726TE

Categories:

Revision as of 13:04, 22 September 2013 editHenriok (talk \| contribs)Extended confirmed users5,398 edits RV - putting sourced statement in in favor of unsourced speculation and original research← Previous edit		Revision as of 18:32, 22 September 2013 edit undoComp.arch (talk \| contribs)Extended confirmed users40,316 edits link MB to Mebibyte (note not Megabyte since not in Megabytes) and KB to Kibibytes. KiB and MB are however discouredgedNext edit →
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	== Design ==		== Design ==
	The A7 features an Apple-designed<ref name="AnandTech-iPhone5s-A7" /> 64-bit<ref name="AnandTech-iPhone5s-64-bit">{{cite web \|first=Anand \|last=Lal Shimpi \|url=http://anandtech.com/show/7335/the-iphone-5s-review/4 \|title=The iPhone 5s Review: The Move to 64-bit \|date= September 17, 2013 \|publisher=AnandTech \|accessdate= September 18, 2013}}</ref> 1.3 GHz<ref name="AnandTech-iPhone5s-A7">{{cite web \|first=Anand \|last=Lal Shimpi \|url=http://anandtech.com/show/7335/the-iphone-5s-review/2 \|title=The iPhone 5s Review: A7 SoC Explained \|publisher=AnandTech \|date= September 17, 2013 \|accessdate= September 18, 2013}}</ref> ]<ref name="AnandTech-iPhone5s-Cyclone">{{cite web \|first=Anand \|last=Lal Shimpi \|url=http://anandtech.com/show/7335/the-iphone-5s-review/3 \|title=The iPhone 5s Review: After Swift Comes Cyclone \|date= September 17, 2013\|publisher=AnandTech \|accessdate= September 18, 2013}}</ref><ref name="LLVM-5s-ARMv8">{{cite web\|url=http://lists.cs.uiuc.edu/pipermail/llvmdev/2013-September/065480.html \|title=],<ref name="AnandTech-iPhone5s-A7" /> called Cyclone,<ref name="AnandTech-iPhone5s-Cyclone" /> and an integrated ] ] (GPU) in a four cluster configuration.<ref name="AnandTech-iPhone5s-GPU">{{cite web \|first=Anand \|last=Lal Shimpi \|url=http://anandtech.com/show/7335/the-iphone-5s-review/7 \|title=The iPhone 5s Review: GPU Architecture \|date= September 17, 2013 \|publisher=AnandTech \|accessdate= September 18, 2013}}</ref> The ARMv8 microarchitecture doubles the number of ] of the A7 compared to the A6.<ref name="Ars: Apple unveils">{{cite web \|last=Cunningham \|first=Andrew \|url= http://arstechnica.com/apple/2013/09/apple-unveils-64-bit-iphone-5s/ \|title=Apple unveils 64-bit iPhone 5S with fingerprint scanner, $199 for 16GB \|publisher=Ars Technica \|date=2013-09-10 \|accessdate=2013-09-12}}</ref> It now has 31 general purpose registers that are each 64-bits wide and 32 floating-point/] registers that are each 128-bits wide.<ref name="AnandTech-iPhone5s-64-bit" /> It has a per-core ] of 64 KB for data and 64 KB for instructions and a shared L2 cache of 1 MB.<ref name="AnandTech-iPhone5s-Cyclone" /> The A7 processor package also incorporates 1 GB of ] DRAM<ref name="TechInsights-iPhone5s">{{cite web \|url= http://www.techinsights.com/apple-iphone-5s/ \|title= Quick Turn Teardown of the Apple iPhone 5s \|publisher=TechInsights \|date=September 20, 2013 \|accessdate=September 20, 2013}}</ref> with a 64-bit wide memory interface.<ref name="AnandTech-iPhone5s-Cyclone" />		The A7 features an Apple-designed<ref name="AnandTech-iPhone5s-A7" /> 64-bit<ref name="AnandTech-iPhone5s-64-bit">{{cite web \|first=Anand \|last=Lal Shimpi \|url=http://anandtech.com/show/7335/the-iphone-5s-review/4 \|title=The iPhone 5s Review: The Move to 64-bit \|date= September 17, 2013 \|publisher=AnandTech \|accessdate= September 18, 2013}}</ref> 1.3 GHz<ref name="AnandTech-iPhone5s-A7">{{cite web \|first=Anand \|last=Lal Shimpi \|url=http://anandtech.com/show/7335/the-iphone-5s-review/2 \|title=The iPhone 5s Review: A7 SoC Explained \|publisher=AnandTech \|date= September 17, 2013 \|accessdate= September 18, 2013}}</ref> ]<ref name="AnandTech-iPhone5s-Cyclone">{{cite web \|first=Anand \|last=Lal Shimpi \|url=http://anandtech.com/show/7335/the-iphone-5s-review/3 \|title=The iPhone 5s Review: After Swift Comes Cyclone \|date= September 17, 2013\|publisher=AnandTech \|accessdate= September 18, 2013}}</ref><ref name="LLVM-5s-ARMv8">{{cite web\|url=http://lists.cs.uiuc.edu/pipermail/llvmdev/2013-September/065480.html \|title=],<ref name="AnandTech-iPhone5s-A7" /> called Cyclone,<ref name="AnandTech-iPhone5s-Cyclone" /> and an integrated ] ] (GPU) in a four cluster configuration.<ref name="AnandTech-iPhone5s-GPU">{{cite web \|first=Anand \|last=Lal Shimpi \|url=http://anandtech.com/show/7335/the-iphone-5s-review/7 \|title=The iPhone 5s Review: GPU Architecture \|date= September 17, 2013 \|publisher=AnandTech \|accessdate= September 18, 2013}}</ref> The ARMv8 microarchitecture doubles the number of ] of the A7 compared to the A6.<ref name="Ars: Apple unveils">{{cite web \|last=Cunningham \|first=Andrew \|url= http://arstechnica.com/apple/2013/09/apple-unveils-64-bit-iphone-5s/ \|title=Apple unveils 64-bit iPhone 5S with fingerprint scanner, $199 for 16GB \|publisher=Ars Technica \|date=2013-09-10 \|accessdate=2013-09-12}}</ref> It now has 31 general purpose registers that are each 64-bits wide and 32 floating-point/] registers that are each 128-bits wide.<ref name="AnandTech-iPhone5s-64-bit" /> It has a per-core ] of 64 ] for data and 64 KB for instructions and a shared L2 cache of 1 ].<ref name="AnandTech-iPhone5s-Cyclone" /> The A7 processor package also incorporates 1 GB of ] DRAM<ref name="TechInsights-iPhone5s">{{cite web \|url= http://www.techinsights.com/apple-iphone-5s/ \|title= Quick Turn Teardown of the Apple iPhone 5s \|publisher=TechInsights \|date=September 20, 2013 \|accessdate=September 20, 2013}}</ref> with a 64-bit wide memory interface.<ref name="AnandTech-iPhone5s-Cyclone" />

	The A7 includes a new ] (ISP), a feature originally introduced in the ], used for functionality related to the camera such as image stabilizing, color correction and light balance.<ref>{{cite web \|url=http://www.apple.com/iphone-5s/design/ \|title=iPhone 5s - Design \|publisher=] \|date=2013-09-10 \|accessdate=2013-09-13}}</ref><ref>{{cite web \|last=Panzarino \|first=Matthew \|url= http://techcrunch.com/2013/09/12/a-photographers-take-on-the-iphone-5s-camera/ \|title=A Photographer’s Take On The iPhone 5S Camera \|publisher=TechCrunch \|date=2013-09-12 \|accessdate=2013-09-13}}</ref> The A7 also includes an area called the ''Secure Enclave'' that stores and protects the data from the iPhone 5s' ] fingerprint sensor.<ref name="Apple iPhone 5s PR" /> The Secure Enclave implements ARM's ]/] technology to keep sensitive data secure.<ref></ref>{{dubious\|Secure Enclave via TrustZone/SecureCore\|date=September 2013}} In a change from the ], the A7 SoC no longer services the accelerometer, gyroscope and compass. In order to reduce power consumption, this functionality has been moved to the new ] motion ] <ref name="AnandTech-iPhone5s-M7">{{cite web \|first=Anand \|last=Lal Shimpi \|url=http://anandtech.com/show/7335/the-iphone-5s-review/8 \|title=The iPhone 5s Review: M7 Motion Coprocessor \|publisher=AnandTech \|date= September 17, 2013 \|accessdate= September 18, 2013}}</ref><ref>{{cite web\|last=Lawler \|first=Richard \|url=http://www.engadget.com/2013/09/10/iphone-5s-m7-coremotion-motion-coprocessor/ \|title=iPhone 5s packs M7 motion-sensing chip, CoreMotion API for more accurate tracking \|publisher=Engadget \|date=2013-09-10 \|accessdate=2013-09-11}}</ref> which appears to be a separate ARM-based microcontroller from ].<ref name="Chipworks-iPhone5s">{{cite web\|url=http://www.chipworks.com/en/technical-competitive-analysis/resources/blog/inside-the-iphone-5s/\|title=Inside the iPhone 5s\|first1=Jason\|last1=Tanner\|first2=Jim\|last2=Morrison\|first3=Dick\|last3=James\|first4=Ray\|last4=Fontaine\|first5=Phil\|last5=Gamache\|publisher=Chipworks\|date=September 20, 2013\|accessdate=September 20, 2013}}</ref>		The A7 includes a new ] (ISP), a feature originally introduced in the ], used for functionality related to the camera such as image stabilizing, color correction and light balance.<ref>{{cite web \|url=http://www.apple.com/iphone-5s/design/ \|title=iPhone 5s - Design \|publisher=] \|date=2013-09-10 \|accessdate=2013-09-13}}</ref><ref>{{cite web \|last=Panzarino \|first=Matthew \|url= http://techcrunch.com/2013/09/12/a-photographers-take-on-the-iphone-5s-camera/ \|title=A Photographer’s Take On The iPhone 5S Camera \|publisher=TechCrunch \|date=2013-09-12 \|accessdate=2013-09-13}}</ref> The A7 also includes an area called the ''Secure Enclave'' that stores and protects the data from the iPhone 5s' ] fingerprint sensor.<ref name="Apple iPhone 5s PR" /> The Secure Enclave implements ARM's ]/] technology to keep sensitive data secure.<ref></ref>{{dubious\|Secure Enclave via TrustZone/SecureCore\|date=September 2013}} In a change from the ], the A7 SoC no longer services the accelerometer, gyroscope and compass. In order to reduce power consumption, this functionality has been moved to the new ] motion ] <ref name="AnandTech-iPhone5s-M7">{{cite web \|first=Anand \|last=Lal Shimpi \|url=http://anandtech.com/show/7335/the-iphone-5s-review/8 \|title=The iPhone 5s Review: M7 Motion Coprocessor \|publisher=AnandTech \|date= September 17, 2013 \|accessdate= September 18, 2013}}</ref><ref>{{cite web\|last=Lawler \|first=Richard \|url=http://www.engadget.com/2013/09/10/iphone-5s-m7-coremotion-motion-coprocessor/ \|title=iPhone 5s packs M7 motion-sensing chip, CoreMotion API for more accurate tracking \|publisher=Engadget \|date=2013-09-10 \|accessdate=2013-09-11}}</ref> which appears to be a separate ARM-based microcontroller from ].<ref name="Chipworks-iPhone5s">{{cite web\|url=http://www.chipworks.com/en/technical-competitive-analysis/resources/blog/inside-the-iphone-5s/\|title=Inside the iPhone 5s\|first1=Jason\|last1=Tanner\|first2=Jim\|last2=Morrison\|first3=Dick\|last3=James\|first4=Ray\|last4=Fontaine\|first5=Phil\|last5=Gamache\|publisher=Chipworks\|date=September 20, 2013\|accessdate=September 20, 2013}}</ref>

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