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{{refimprove|date=October 2009}} {{refimprove|date=October 2009}}
] ]
The '''Efficeon''' processor is ]'s second-generation ] ] design released in 2004 which employs a software engine ] (CMS) to convert code written for ] processors to the native ] of the chip. Like its predecessor, the ] (a ] VLIW architecture), Efficeon stresses computational efficiency, low power consumption, and a low thermal footprint. The '''Efficeon''' (stylized as '''efficēon''') processor is ]'s second-generation ] ] design released in 2004 which employs a software engine ] (CMS) to convert code written for ] processors to the native ] of the chip. Like its predecessor, the ] (a ] VLIW architecture), Efficeon stresses computational efficiency, low power consumption, and a low thermal footprint.


==Processor== ==Processor==
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Two generations of this chip were produced. The first generation (TM8600) was manufactured using a ] 0.13 micrometre process and produced at speeds up to 1.2 ]. The second generation (TM8800 and TM8820) was manufactured using a ] 90 nm process and produced at speeds ranging from 1 GHz to 1.7 GHz. Two generations of this chip were produced. The first generation (TM8600) was manufactured using a ] 0.13 micrometre process and produced at speeds up to 1.2 ]. The second generation (TM8800 and TM8820) was manufactured using a ] 90 nm process and produced at speeds ranging from 1 GHz to 1.7 GHz.


Internally, the Efficeon has two ]s, two load/store/add units, two execute units, two ]/]/]/] units, one ], one alias unit, and one control unit. The VLIW core can execute a 256-bit VLIW instruction per cycle, which is called a molecule and has room to store eight 32-bit instructions (called atoms) per cycle. Internally, the Efficeon has two ]s, two load/store/add units, two execute units, two ]/]/]/] units, one ], one alias unit, and one control unit. The VLIW core can execute a 256-bit VLIW instruction per cycle, which is called a molecule, and has room to store eight 32-bit instructions (called atoms) per cycle.


The Efficeon has a 128 KB L1 instruction cache, a 64 KB L1 data cache and a 1 MB L2 cache. All caches are on die. The Efficeon has a 128 KB L1 instruction cache, a 64 KB L1 data cache and a 1 MB L2 cache. All caches are on die.


Additionally the Efficeon CMS (code morphing software) reserves a small portion of main memory (typically 32 MB) for its translation cache of dynamically translated x86 instructions. Additionally, the Efficeon CMS (code morphing software) reserves a small portion of main memory (typically 32 MB) for its translation cache of dynamically translated x86 instructions.


==Products== ==Products==
] ]
* ] A532 * ] A532 (was also sold as IRu Stilo 1715L, Fudita Smart TM1000)
* Hewlett-Packard ] T5710 * ] t5710 ]
* ] ]<ref></ref> (first generation) * ] ]<ref></ref> (first generation)
* Orion Multisystem ] * Orion Multisystem ]
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Latest revision as of 18:44, 7 September 2024

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A Transmeta Efficeon processor

The Efficeon (stylized as efficēon) processor is Transmeta's second-generation 256-bit VLIW design released in 2004 which employs a software engine Code Morphing Software (CMS) to convert code written for x86 processors to the native instruction set of the chip. Like its predecessor, the Transmeta Crusoe (a 128-bit VLIW architecture), Efficeon stresses computational efficiency, low power consumption, and a low thermal footprint.

Processor

Efficeon most closely mirrors the feature set of Intel Pentium 4 processors, although, like AMD Opteron processors, it supports a fully integrated memory controller, a HyperTransport IO bus, and the NX bit, or no-execute x86 extension to PAE mode. NX bit support is available starting with CMS version 6.0.4.

Efficeon's computational performance relative to mobile CPUs like the Intel Pentium M is thought to be lower, although little appears to be published about the relative performance of these competing processors.

Efficeon came in two package types: a 783- and a 592-contact ball grid array (BGA). Its power consumption is moderate (with some consuming as little as 3 watts at 1 GHz and 7 watts at 1.5 GHz), so it can be passively cooled.

Two generations of this chip were produced. The first generation (TM8600) was manufactured using a TSMC 0.13 micrometre process and produced at speeds up to 1.2 GHz. The second generation (TM8800 and TM8820) was manufactured using a Fujitsu 90 nm process and produced at speeds ranging from 1 GHz to 1.7 GHz.

Internally, the Efficeon has two arithmetic logic units, two load/store/add units, two execute units, two floating-point/MMX/SSE/SSE2 units, one branch prediction unit, one alias unit, and one control unit. The VLIW core can execute a 256-bit VLIW instruction per cycle, which is called a molecule, and has room to store eight 32-bit instructions (called atoms) per cycle.

The Efficeon has a 128 KB L1 instruction cache, a 64 KB L1 data cache and a 1 MB L2 cache. All caches are on die.

Additionally, the Efficeon CMS (code morphing software) reserves a small portion of main memory (typically 32 MB) for its translation cache of dynamically translated x86 instructions.

Products

1 GHz Efficeon TM8600 used on Sharp Mebius MURAMASA / PC-MM2

References

  1. Microsoft brings Vista to developing world PCs

External links

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