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== PAE Xeon only ==
== "offset within page" does not come from the page-table entry ==

The phrase should surely be . <!-- Template:Unsigned IP --><small class="autosigned">—&nbsp;Preceding ] comment added by ] (]) 23:56, 12 October 2016 (UTC)</small> <!--Autosigned by SineBot-->


It should be made clear the only IA-32 processor which supported Physical Address Extension as defined by Intel was Xeon. PAE requires BOTH 36 address registers AND 36bit data bus for RAM.
: You are of course correct - and nice catch, that's been on the page for a long time. You can of course make the change yourself if you want. Be ] ! ] (]) 03:08, 13 October 2016 (UTC)


All IA-32 processors had at most a 32bit data bus. 36 address registers only allows paging - it is not PAE support.
== "Paging and Virtual Memory" ==


Only Xeon had 36bits for RAM. Xeon supported 8GB RAM total. The 8GB was split into 2x 4GB memory banks accessed one bank at a time. The 32bit + 4bit bus allowed a segment selector.
Anyone reading this article should have at least a basic understanding of the concept of ] in my opinion. And perhaps more importantly, the added section ''still'' requires such an understanding, because it provides no explanation of what paging and pages are to other readers. Therefore I don't see it as an improvement. It also seems to be copied and pasted from the source (judging from the excessive line breaks) and therefore not allowed.--] ] 19:40, 10 April 2017 (UTC)
(Xeon was technically a 36bit CPU).


] (]) 23:25, 10 May 2020 (UTC)
:It also didn't " how PAE works in IA-32" - the only thing it said about PAE is that "IA-32 architecture’s paging mechanism includes extensions that support Physical Address Extensions (PAE) to address physical address space greater than 4 GBytes." That says what PAE does, but doesn't say how it does it. The article ''already'' says what it does (in the lede, it says " It defines a ] hierarchy of three levels, with table entries of 64 bits each instead of 32, allowing these CPUs to access a physical ] larger than 4&nbsp;]s (2<sup>32</sup> bytes)."), ''and'' it later says how it does it (a quick mention in "Design", and a long description in "Page table structures"). ] (]) 19:55, 10 April 2017 (UTC)


:No, as that's rubbish. Where's the definition of that per Intel? The article currently has it right ] - the chipset and motherboard etc have to also support 36 bit, which I know myself certainly some non-Xeons did. <span class="vcard"><span class="fn">]</span>; ]</span> 22:09, 1 September 2020 (UTC)
:: I'm glad I'm not the only one. I couldn't see where it "explained how PAE works" at all.
:: Worse: As suspected by Jasper Deng, the disputed material is a direct copy from volume 1, section 3.3.2, of the . There is no doubt or ambiguity about that. The editor even copied the bulleted list from the Intel book as if it was ordinary text, resulting in "inline bullets". I have left a copyvio warning on their talk page.
:: What is especially odd here is that the same editor, {{userlinks|PastieFace}}, had previously what was basically a CN tag on ], claiming that a cited reference referred only to the Pentium Pro and that any statements about later processors were CN. Yet this editor is clearly aware of this Intel reference which defines PAE as part of the IA-32 architecture, not specific to any processor.
:: Both of these articles have been the target of much harassment over the last few years. I note that these recent instances happened shortly after I got a from our old friend and long-time sockpuppet Janagewen. Whether there's a connection there or not, I think PastieFace's future attempts can be ignored on ] grounds, and should be checked for ] as well. ] (]) 07:59, 11 April 2017 (UTC)
{{ping|PastieFace}} If you bothered to look at the section on "Operating system support" you'll see that it's ''not'' a Windows-specific thing. And virtual memory has everything to do with it: each virtual address space remains 32-bit even if the physical memory is bigger, as your edit even mentions. If you do not have a good understanding of this concept, I suggest you avoid this topic.--] ] 20:28, 12 April 2017 (UTC)


== First Linux kernel to support PAE ==
:Furthermore, if you don't have paging virtual memory enabled, PAE doesn't even exist - PAE involves a modified form of the page table, with larger page table entries capable of providing more bits of physical address, expanding the physical addresses generated for virtual addresses from 32 bits to 36 bits. ] (]) 20:45, 12 April 2017 (UTC)
:: And wider on x64 processors while in long mode. ] (]) 21:11, 12 April 2017 (UTC)


The section says 2.3.23 but under the old scheme odd numbers were development kernels (2.2 series was the release, 2.3 was concurrent and the development space for what would ship as 2.4). Would probably make sense to also mention which kernel was the first to ship with PAE, since no released distro would use a development kernel. --] (]) 03:44, 1 May 2022 (UTC)
:Further²more: PF claims it is Intel-only. That is wrong. PAE has been supported by AMD CPUs since the Athlon (K7) and continues in the K8, even when the latter is in legacy mode (ie running as an x86 CPU). It is true that AMD's support for PAE came several years later than Intel's: Intel had it in the Pentium Pro, late 1995, while AMD didn't have it until the Athlon, mid 1999. So, yes, ''for a time,'' Intel supported PAE while AMD did not. But that time is now ''over 15 years ago!''
:I wish I could quote a K7-era AMD Architecture manual, but I can't find one. The oldest I have is the original hardcopy set for the AMD64 architecture, which does show that PAE is available on the K8 in legacy mode, but that isn't definitive for the K7. The online sources I've found are more recent still, but one would hope that they would at least disabuse PF of the notion that AMD doesn't support PAE at all on ''any'' platform. (See , section 5.2.3 for legacy mode. For long mode, see 5.3: ''"Because PAE is always enabled in long mode ..."''
: On the bright side, PastiF's mistaken ideas have suggested to me a new diagram that may eliminate misconceptions like ''" once a process hit the 4GB limit, IA-32 CPU would start paging in and out of RAM using internal registers., that's what PAE is."'' (from PastieFace's
to my talk page) (No, the CPU does not do that, and that isn't what PAE is.) ] (]) 21:11, 12 April 2017 (UTC)

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PAE Xeon only

It should be made clear the only IA-32 processor which supported Physical Address Extension as defined by Intel was Xeon. PAE requires BOTH 36 address registers AND 36bit data bus for RAM.

All IA-32 processors had at most a 32bit data bus. 36 address registers only allows paging - it is not PAE support.

Only Xeon had 36bits for RAM. Xeon supported 8GB RAM total. The 8GB was split into 2x 4GB memory banks accessed one bank at a time. The 32bit + 4bit bus allowed a segment selector. (Xeon was technically a 36bit CPU).

Onzite. (talk) 23:25, 10 May 2020 (UTC)

No, as that's rubbish. Where's the definition of that per Intel? The article currently has it right Physical Address Extension#Hardware support - the chipset and motherboard etc have to also support 36 bit, which I know myself certainly some non-Xeons did. Widefox; talk 22:09, 1 September 2020 (UTC)

First Linux kernel to support PAE

The section says 2.3.23 but under the old scheme odd numbers were development kernels (2.2 series was the release, 2.3 was concurrent and the development space for what would ship as 2.4). Would probably make sense to also mention which kernel was the first to ship with PAE, since no released distro would use a development kernel. --97.115.191.42 (talk) 03:44, 1 May 2022 (UTC)

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