| Revision as of 13:18, 3 November 2008 editMac (talk | contribs)23,294 edits ←Created page with 'Typically, amorphous silicon thin-film cells use a p-i-n structure, whereas CdTe cells use an n-i-p structure. The basic scenario is as follows: A thre...' | Revision as of 13:18, 3 November 2008 edit undoMac (talk | contribs)23,294 editsmNo edit summaryNext edit → | ||
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| The basic scenario is as follows: A three-layer sandwich is created, with a middle intrinsic (i-type or undoped) layer between an n-type layer and a p-type layer. This geometry sets up an electric field between the p- and n-type regions that stretches across the middle intrinsic resistive region. Light generates free electrons and holes in the intrinsic region, which are then separated by the electric field. | The basic scenario is as follows: A three-layer sandwich is created, with a middle intrinsic (i-type or undoped) layer between an n-type layer and a p-type layer. This geometry sets up an electric field between the p- and n-type regions that stretches across the middle intrinsic resistive region. Light generates free electrons and holes in the intrinsic region, which are then separated by the electric field. | ||
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== p-i-n== | ||
| In the p-i-n amorphous silicon (a-Si) cell, the top layer is p-type a-Si, the middle layer is intrinsic silicon, and the bottom layer is n-type a-Si. Amorphous silicon has many atomic-level electrical defects when it is highly conductive. So very little current would flow if an a-Si cell had to depend on diffusion. However, in a p-i-n cell, current flows because the free electrons and holes are generated within the influence of an electric field, rather than having to move toward the field. | In the p-i-n amorphous silicon (a-Si) cell, the top layer is p-type a-Si, the middle layer is intrinsic silicon, and the bottom layer is n-type a-Si. Amorphous silicon has many atomic-level electrical defects when it is highly conductive. So very little current would flow if an a-Si cell had to depend on diffusion. However, in a p-i-n cell, current flows because the free electrons and holes are generated within the influence of an electric field, rather than having to move toward the field. | ||
Revision as of 13:18, 3 November 2008
Typically, amorphous silicon thin-film cells use a p-i-n structure, whereas CdTe cells use an n-i-p structure.
The basic scenario is as follows: A three-layer sandwich is created, with a middle intrinsic (i-type or undoped) layer between an n-type layer and a p-type layer. This geometry sets up an electric field between the p- and n-type regions that stretches across the middle intrinsic resistive region. Light generates free electrons and holes in the intrinsic region, which are then separated by the electric field.
p-i-n
In the p-i-n amorphous silicon (a-Si) cell, the top layer is p-type a-Si, the middle layer is intrinsic silicon, and the bottom layer is n-type a-Si. Amorphous silicon has many atomic-level electrical defects when it is highly conductive. So very little current would flow if an a-Si cell had to depend on diffusion. However, in a p-i-n cell, current flows because the free electrons and holes are generated within the influence of an electric field, rather than having to move toward the field.
n-i-p
In a CdTe cell, the device structure is similar to the a-Si cell, except the order of layers is flipped upside down. Specifically, in a typical CdTe cell, the top layer is p-type cadmium sulfide (CdS), the middle layer is intrinsic CdTe, and the bottom layer is n-type zinc telluride (ZnTe).
References
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