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| In ] design, '''library''' often refers to a collection of cells, macros or functional units that perform common operations and are used to build more complex logic blocks. |
In ] design, '''library''' often refers to a collection of cells, macros or functional units that perform common operations and are used to build more complex logic blocks. | ||
| A standard cell library is a collection of low level logic functions such as AND, OR, INVERT, flip-flops, latches and buffers. These cells are realized as fixed height, variable width full custom cells. The key aspect with these libraries is that they are of a fixed height, which enables them to be placed in rows, easing the process of automated digital layout. The cells are typically optimised full custom layouts, which maximise delays and minimise area. | |||
| A typical standard cell library contains two main components. | |||
| 1) Timing Abstract (This is generally in the Synopsys Liberty format) - This provides functional definitions, timing, power and noise information for each cell. | |||
| 2) Layout Abstract - These contain reduced information about the cell layouts, which is sufficent for automated "Place and Route" tools | |||
| They also may contain the following aspects | |||
| 1) A full layout of the cells | |||
| 2) Spice models of the cells | |||
| 3) Verilog models or VHDL Vital models | |||
| An example is a simple XOR logic gate, which can be formed from OR, INVERT and AND gates. <!-- I believe this is a relevant example. If someone can verify this, please feel free to remove this comment --> | An example is a simple XOR logic gate, which can be formed from OR, INVERT and AND gates. <!-- I believe this is a relevant example. If someone can verify this, please feel free to remove this comment --> | ||
| {{Electro-stub}} | {{Electro-stub}} | ||
Revision as of 00:37, 27 January 2007
In electronic design, library often refers to a collection of cells, macros or functional units that perform common operations and are used to build more complex logic blocks. A standard cell library is a collection of low level logic functions such as AND, OR, INVERT, flip-flops, latches and buffers. These cells are realized as fixed height, variable width full custom cells. The key aspect with these libraries is that they are of a fixed height, which enables them to be placed in rows, easing the process of automated digital layout. The cells are typically optimised full custom layouts, which maximise delays and minimise area. A typical standard cell library contains two main components.
1) Timing Abstract (This is generally in the Synopsys Liberty format) - This provides functional definitions, timing, power and noise information for each cell. 2) Layout Abstract - These contain reduced information about the cell layouts, which is sufficent for automated "Place and Route" tools
They also may contain the following aspects
1) A full layout of the cells 2) Spice models of the cells 3) Verilog models or VHDL Vital models
An example is a simple XOR logic gate, which can be formed from OR, INVERT and AND gates.
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((electro-dictionaries))