| Revision as of 21:20, 9 September 2006 edit86.143.175.215 (talk) →[]← Previous edit | Revision as of 22:06, 9 September 2006 edit undoSagaciousuk (talk | contribs)Extended confirmed users, Pending changes reviewers, Rollbackers6,368 edits Reverted edits by 86.143.175.215 (talk) using VPNext edit → | ||
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| * Bus Width 8 bits data, 16 bits address | * Bus Width 8 bits data, 16 bits address | ||
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| * Number of Transistors |
* Number of Transistors 6,000 at 6 µm | ||
| * Addressable memory 64 KiB | * Addressable memory 64 KiB | ||
| * 10X the performance of the 8008 | * 10X the performance of the 8008 | ||
Revision as of 22:06, 9 September 2006
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This generational and chronological list of Intel microprocessors attempts to present all of Intel's processors (µPs) from the pioneering 4-bit 4004 (1971) to the present high-end offerings, the 64-bit Itanium 2 (2002) and Pentium 4F with EM64T (2004). Concise technical data are given for each product.
Note: For a list of Intel's microcontrollers (µCs), see Intel microcontrollers.
The 4-bit processors
Intel 4004: 1st single-chip µP
- Introduced November 15, 1971
- Clock speed 740 kHz
- 0.06 MIPS
- Bus Width 4 bits (multiplexed address/data due to limited pins)
- PMOS
- Number of Transistors 2,300 at 10 µm
- Addressable Memory 640 bytes
- Program Memory 4 KiB
- One of the earliest Commercial Microprocessors (cf. Four Phase Systems AL1, F14 CADC)
- Originally designed to be used in Busicom calculator
- A 4004 formed the "brain" of the Pioneer 10 space probe, launched in March 1972. The projected mission lifetime was just over two years, but when the probe finally moved out of radio contact range in 2003, the computer and most of the other on-board electronic systems were still functioning.
- Trivia: The original goal was to equal the clock speed of the IBM 1620 (1 MHz); this was not quite met.
4040
- Introduced 4th Qtr, 1974
- Clock speed of 500 kHz to 740 kHz using 4 to 5.185 MHz crystals
- 0.06 MIPS
- Bus Width 4 bits (multiplexed address/data due to limited pins)
- PMOS
- Number of Transistors 3,000 at 10 µm
- Addressable Memory 640 bytes
- Program Memory 8 KiB
- Interrupts
- Enhanced version of 4004
MCS-40 Family :
4001-2048-bit (256 x 8) ROM w/4-bit I/O Port
4207/4209/4211-General Purpose Byte Input Port
4265-Programmable General Purpose I/O Device
4269-Programmable Keyboard Display Device
4289-Standard Memory Interface for MCS-4/40
4308-8192-bit (1024 x 8) ROM w 4-bit IO Ports
4316-16384-bit (2048 x 8) Static ROM
4801-5.185 MHz Clock Generator Crystal for 4004_4201A or 4040/4201A CPU Set
The 8-bit processors
8008
- Introduced April 1, 1972
- Clock speed 500 kHz (8008-1: 800 kHz)
- 0.05 MIPS
- Bus Width 8 bits (multiplexed address/data due to limited pins)
- PMOS
- Number of Transistors 3,500 at 10 µm
- Addressable memory 16 KiB
- Typical in dumb terminals, general calculators, bottling machines
- Developed in tandem with 4004
- Originally intended for use in the Datapoint 2200 terminal
8080
- Introduced April 1, 1974
- Clock speed 2 MHz
- 0.64 MIPS
- Bus Width 8 bits data, 16 bits address
- NMOS
- Number of Transistors 6,000 at 6 µm
- Addressable memory 64 KiB
- 10X the performance of the 8008
- Used in the Altair 8800, Traffic light controller, cruise missile
- Required six support chips versus 20 for the 8008
8085
- Introduced March 1976
- Clock speed 5 MHz
- 0.37 MIPS
- Bus Width 8 bits data, 16 bits address
- Number of Transistors 6,500 at 3 µm
- Assembly language downwards compatible with 8080.
- Used in Toledo scale. Also was used as a computer peripheral controller - modems, harddisks, etc...
- CMOS 80C85 in Radio Shack Model 100 portable.
- High level of integration, operating for the first time on a single 5 volt power supply, from 12 volts previously. Also featured two serial I/O connections.
MCS-85 Family : 8101 1024-bit(256 x 4)Static RAM w/Separate I/O 8102 1024-bit(1024 x 1)Static RAM w/Separate I/O 8107 4096-bit(4096 x 1)Dynamic RAM 8111 1024-bit(256 x 4)Static RAM w/Common I/O 8155 2048-bit(256 x 8)Static RAM w/I/O Ports and Timer,CE ActiveLow 8156 2048-bit(256 x 8)Static RAM w/I/O Ports and Timer,CE Active High 8185 8192-bit (1024 x 8) Static RAM for MCS-85™ 8202 Dynamic RAM Controller 8205 High Speed 1 out of 8 Binary Decoder 8210 Quad MOS Driver and Clock driver for 8107 DRAM 8212 8-bit Input/Output Port 8214 Priority Interrupt Control Unit (PICU) 8216 4-bit Non-Inverting Parallel Bi-Directional BUS Driver 8218 Bipolar Microcomputer Bus Controller for MCS-80™ 8219 Bipolar Microcomputer Bus Controller for MCS-85™ 8222 Refresh Controller for 4K DRAMs 8224 Single Chip Clock Generator/Driver for 8080A CPU 8226 4-bit Inverting Parallel Bi-Directional BUS Driver 3rd Qtr 8228 System Controller and Bus Driver for 8080A CPU 8231 Arithmetic Processing Unit 1980 8232 Floating Point Processor 1980 8237 High Performance Programmable DMA Controller 8238 System Controller and Bus Driver w/Advanced IOW/MEMW 8243 MCS-48™ Input/Output Expander 8251 Programmable Communication Interface 8253 Programmable Interval Timer 8255 Programmable Peripheral Interface 8257 Programmable DMA Controller 8259 Programmable Interrupt Controller 8271 Programmable Floppy Disk Controller 8272 Single/Double Density Floppy Disk Controller 8273 Programmable HDLC/SDLC Protocol Controller 8275 Programmable CRT (Video) Controller 8278 Programmable Keyboard Interface 8279 Programmable Keyboard / Display Controller 8282 8-bit Non-Inverting Latch with Output Buffer 8283 8-bit Inverting Latch with Output Buffer 8284 Clock Generator and Driver for iAPX86/88 Processors 8286 8-bit Non-Inverting Bus Transceiver 8287 8-bit Inverting Bus Transceiver 8288 Bipolar Bus Controller for iAPX 86/88 Processors 8289 Bus Arbiter iAPX 86/88 Processors 8291 GPIB Talker/ Listener 8292 GPIB Controller 8293 GPIB Transceiver 8294 Data Encryption Unit 8295 Dot Matrix Printer Controller 8302 2048-bit (256 x 8) Static ROM 8308 8096-bit (1024 x 8) Static ROM 8316 16384-bit (2048 x 8) Static ROM 8355 16,384-bit (2048 x 8) ROM with I/O 8604 4096-bit (512 x 8) PROM 8641 Universal Peripheral Interface 8-Bit Microcomputer w/8,192-bit (1024 x 8) PROM, 512-bit (64 x 8) RAM and I/O 8702 2048-bit (256 x 8) EPROM 8704 4096-bit (512 x 8) EPROM 8708 8192-bit (1024 x 8) EPROM 8741 Universal Peripheral Interface 8-Bit Microcomputer w/8,192-bit (1024 x 8) EPROM, 512-bit (64 x 8) RAM and I/O 8755 16,384-bit (2048 x 8) EPROM with I/O 1976-77 8755A16,384-bit (2048 x 8) EPROM with I/O
The bit slice processor
3000 Family
- Introduced 3rd Qtr, 1974
- Members of the family
- 3001 (Microcontrol Unit)
- 3002 (2-bit Arithmetic Logic Unit slice)
- 3003 (Look-ahead Carry Generator)
- 3212 (Multimode Latch Buffer)
- 3214 (Interrupt Control Unit)
- 3216 (Parallel Bi-directional Bus Driver)
- Bus Width 2-n bits data/address (depending on number of slices used)
The 16-bit processors: Origin of x86
8086
- Introduced June 8, 1978
- Clock speeds:
- 5 MHz with 0.33 MIPS
- 8 MHz with 0.66 MIPS
- 10 MHz with 0.75 MIPS
- Bus Width 16 bits data, 20 bits address
- Number of Transistors 29,000 at 3 µm
- Addressable memory 1 megabyte
- 10X the performance of 8080
- Used in portable computing
- Used segment registers to access more than 64 KiB of data at once, bane of programmers' existence for years to come
8088
- Introduced June 1, 1979
- Clock speeds:
- 5 MHz with 0.33 MIPS
- 8 MHz with 0.75 MIPS
- Internal architecture 16 bits
- External bus Width 8 bits data, 20 bits address
- Number of Transistors 29,000 at 3 µm
- Addressable memory 1 megabyte
- Identical to 8086 except for its 8 bit external bus (hence an 8 instead of a 6 at the end)
- Used in IBM PCs and PC clones
iAPX 432 (chronological entry)
- Introduced January 1, 1981
- Multi-chip CPU; Intel's first 32-bit microprocessor
- See main entry
80186
- Introduced 1982
- Used mostly in embedded applications - controllers, point-of-sale systems, terminals, and the like
- Included two timers, a DMA controller, and an interrupt controller on the chip in addition to the processor
- Later renamed the iAPX 186
80188
- A version of the 80186 with an 8-bit external data bus
- Later renamed the iAPX 188
80286
- Introduced February 1, 1982
- Clock speeds:
- 6 MHz with 0.9 MIPS
- 8 MHz, 10 MHz with 1.5 MIPS
- 12.5 MHz with 2.66 MIPS
- Bus Width 16 bits
- Included memory protection hardware to support multitasking operating systems with per-process address space
- Number of Transistors 134,000 at 1.5 µm
- Addressable memory 16 megabytes
- Added protected-mode features to 8086 with essentially the same instruction set
- 3-6X the performance of the 8086
- Widely used in PC clones at the time
- Can scan the Encyclopædia Britannica in 45 seconds
32-bit processors: The non-x86 µPs
iAPX 432
- Introduced January 1, 1981 as Intel's first 32-bit microprocessor
- Object/capability architecture
- Microcoded operating system primitives
- One terabyte virtual address space
- Hardware support for fault tolerance
- Two-chip General Data Processor (GDP), consists of 43201 and 43202
- 43203 Interface Processor (IP) interfaces to I/O subsystem
- 43204 Bus Interface Unit (BIU) simplifies building multiprocessor systems
- 43205 Memory Control Unit (MCU)
- Architecture and execution unit internal data paths 32 bit
- Clock speeds:
- 5 MHz
- 7 MHz
- 8 MHz
i960 aka 80960
- Introduced April 5, 1988
- RISC-like 32-bit architecture
- predominantly used in embedded systems
- Evolved from the capability processor developed for the BiiN joint venture with Siemens
- Many variants identified by two-letter suffixes.
80386SX (chronological entry)
- Introduced June 16, 1988
- See main entry
80376 (chronological entry)
- Introduced January 16, 1989
- See main entry
i860 aka 80860
- Introduced February 27, 1989
- Intel's first superscalar processor
- RISC 32/64-bit architecture, with pipeline characteristics very visible to programmer
- Used in Intel Paragon massively parallel supercomputer
XScale
- Introduced August 23, 2000
- 32-bit RISC microprocessor based on the ARM architecture
- Many variants, such as the PXA2xx applications processors, IOP3xx I/O processors and IXP2xxx and IXP4xx network processors.
32-bit processors: The 80386 range
80386DX
- Introduced October 17, 1985
- Clock speeds:
- Bus Width 32 bits
- Number of Transistors 275,000 at 1 µm
- Addressable memory 4 gigabytes
- Virtual memory 64 terabyte
- First x86 chip to handle 32-bit data sets
- Reworked and expanded memory protection support including paged virtual memory and virtual-86 mode, features required by Windows 95 and OS/2 Warp
- Used in Desktop computing
- Can address enough memory to manage an eight-page history of every person on earth
- Can scan the Encyclopædia Britannica in 12.5 seconds
80960 (i960) (chronological entry)
- Introduced April 5, 1988
- See main entry
80386SX
- Introduced June 16, 1988
- Clock speeds:
- 16 MHz with 2.5 MIPS
- 20 MHz with 2.5 MIPS, 25 MHz with 2.7 MIPS, introduced 25 January 1989
- 33 MHz with 2.9 MIPS, introduced 26 October 1992
- Internal architecture 32 bits
- External data bus width 16 bits
- External address bus width 24 bits
- Number of Transistors 275,000 at 1 µm
- Addressable memory 16MB
- Virtual memory 1 terabyte
- Narrower buses enable low-cost 32-bit processing
- Built-in multitasking
- Used in entry-level desktop and portable computing
80376
- Introduced January 16, 1989; Discontinued June 15, 2001
- Variant of 386 intended for embedded systems
- No "real mode", starts up directly in "protected mode"
- Replaced by much more successful 80386EX from 1994
80860 (i860) (chronological entry)
- Introduced February 27, 1989
- See main entry
80486DX (chronological entry)
- Introduced April 10, 1989
- See main entry
80386SL
- Introduced October 15, 1990
- Clock speeds:
- 20 MHz with 4.21 MIPS
- 25 MHz with 5.3 MIPS, introduced 30 September 1991
- Internal architecture 32 bits
- External bus width 16 bits
- Number of Transistors 855,000 at 1 µm
- Addressable memory 4 gigabytes
- Virtual memory 1 terabyte
- First chip specifically made for portable computers because of low power consumption of chip
- Highly integrated, includes cache, bus, and memory controllers
80486SX/DX2/SL, Pentium, 80486DX4 (chronological entries)
- Introduced 1991–1994
- See main entries
80386EX
- Introduced August 1994
- Variant of 80386SX intended for embedded systems
- Static core, i.e. may run as slowly (and thus, power efficiently) as desired, down to full halt
- On-chip peripherals:
- Clock and power mgmt
- Timers/counters
- Watchdog timer
- Serial I/O units (sync and async) and parallel I/O
- DMA
- RAM refresh
- JTAG test logic
- Significantly more successful than the 80376
- Used aboard several orbiting satellites and microsatellites
- Used in NASA's FlightLinux project
32-bit processors: The 80486 range
80486DX
- Introduced April 10, 1989
- Clock speeds:
- Bus Width 32 bits
- Number of Transistors 1.2 million at 1 µm; the 50 MHz was at 0.8 µm
- Addressable memory 4 gigabytes
- Virtual memory 1 terabyte
- Level 1 cache on chip
- Math coprocessor on chip
- 50X performance of the 8088
- Used in Desktop computing and servers
- Family 4 model 3
80386SL (chronological entry)
- Introduced October 15, 1990
- See main entry
80486SX
- Introduced April 22, 1991
- Clock speeds:
- 16 MHz with 13 MIPS
- 20 MHz with 16.5 MIPS, introduced 16 September 1991
- 25 MHz with 20 MIPS (12 SPECint92), introduced 16 September 1991
- 33 MHz with 27 MIPS (15.86 SPECint92), introduced 21 September 1992
- Bus Width 32 bits
- Number of Transistors 1.185 million at 1 µm and 900,000 at 0.8 µm
- Addressable memory 4 gigabytes
- Virtual memory 1 terabyte
- Identical in design to 486DX but without math coprocessor
- Used in low-cost entry to 486 CPU desktop computing
- Upgradable with the Intel OverDrive processor
- Family 4 model 2
80486DX2
- Introduced March 3, 1992
- Clock speeds:
- Bus Width 32 bits
- Number of Transistors 1.2 million at 0.8 µm
- Addressable memory 4 gigabytes
- Virtual memory 1 terabyte
- Used in high performance, low cost desktops
- Uses "speed doubler" technology where the microprocessor core(Internal Clock) runs at twice the speed of the bus(External Clock)
- Family 4 model 7
80486SL
- Introduced November 9, 1992
- Clock speeds:
- 20 MHz with 15.4MIPS
- 25 MHz with 19 MIPS
- 33 MHz with 25 MIPS
- Bus Width 32 bits
- Number of Transistors 1.4 million at 0.8 µm
- Addressable memory 64 megabytes
- Virtual memory 1 terabyte
- Used in notebook computers
- Family 4 model 3
Pentium (chronological entry)
- Introduced March 22, 1993
- See main entry
80486DX4
- Introduced March 7, 1994
- Clock speeds:
- 75 MHz with 53 MIPS (41.3 SPECint92, 20.1 SPECfp92 on Micronics M4P 256 KiB L2)
- 100 MHz with 70.7 MIPS (54.59 SPECint92, 26.91 SPECfp92 on Micronics M4P 256 KiB L2)
- Number of Transistors 1.6 million at 0.6 µm
- Bus width 32 bits
- Addressable memory 4 gigabytes
- Virtual memory 64 terabytes
- Pin count 168 PGA Package, 208 sq ftP Package
- Die size 345 mm²
- Used in high performance entry-level desktops and value notebooks
- Family 4 model 8
32-bit processors: The Pentium ("I")
Pentium ("Classic")
- Bus width 64 bits
- System bus speed 60 or 66 MHz
- Address bus 32 bits
- Addressable Memory 4 gigabytes
- Virtual Memory 64 terabytes
- Superscalar architecture brought 5X the performance of the 33 MHz 486DX processor
- Runs on 5 volts
- Used in desktops
- 16 KiB of L1 cache
- P5 - 0.8 µm process technology
- Introduced March 22, 1993
- Number of transistors 3.1 million
- Socket 4 273 pin PGA processor package
- Package dimensions 2.16" x 2.16"
- Family 5 model 1
- Variants
- 60 MHz with 100 MIPS (70.4 SPECint92, 55.1 SPECfp92 on Xpress 256 KiB L2)
- 66 MHz with 112 MIPS (77.9 SPECint92, 63.6 SPECfp92 on Xpress 256 KiB L2)
- P54 - 0.6 µm process technology
- P54C - 0.35 µm process technology
80486DX4 (chronological entry)
- Introduced March 7, 1994
- See main entry
80386EX (Intel386 EX) (chronological entry)
- Introduced August 1994
- See main entry
Pentium Pro (chronological entry)
- Introduced November 1995
- See main entry
Pentium MMX
- P55C - 0.35 µm process technology
- Introduced January 8, 1997
- Intel MMX instructions
- Socket 7 296/321 pin PGA (pin grid array) package
- 32 KiB L1 cache
- Number of transistors 4.5 million
- System bus speed 66 MHz
- Basic P55C is family 5 model 4, mobile are family 5 model 7 and 8
- Variants
- 166 MHz Introduced January 8, 1997
- 200 MHz Introduced January 8, 1997
- 233 MHz Introduced June 2, 1997
- 166 MHz (Mobile) Introduced January 12, 1998
- 200 MHz (Mobile) Introduced September 8, 1997
- 233 MHz (Mobile) Introduced September 8, 1997
- 266 MHz (Mobile) Introduced January 12, 1998
- 300 MHz (Mobile) Introduced January 7, 1999
32-bit processors: P6/Pentium M microarchitecture
Pentium Pro
- Introduced November 1, 1995
- Precursor to Pentium II and III
- Primarily used in server systems
- Socket 8 processor package (387 pins) (Dual SPGA)
- Number of transistors 5.5 million
- Family 6 model 1
- 0.6 µm process technology
- 16 KiB L1 cache
- 256 KiB integrated L2 cache
- 60 MHz system bus speed
- Variants
- 150 MHz
- 0.35 µm process technology, or 0.35 µm CPU with 0.6 µm L2 cache
- Number of transistors 5.5 million
- 512 KiB or 256 KiB integrated L2 cache
- 60 or 66 MHz system bus speed
- Variants
- 166 MHz (66 MHz bus speed, 512 KiB 0.35 µm cache) Introduced November 1, 1995
- 180 MHz (60 MHz bus speed, 256 KiB 0.6 µm cache) Introduced November 1, 1995
- 200 MHz (66 MHz bus speed, 256 KiB 0.6 µm cache) Introduced November 1, 1995
- 200 MHz (66 MHz bus speed, 512 KiB 0.35 µm cache) Introduced November 1, 1995
- 200 MHz (66 MHz bus speed, 1 MiB 0.35 µm cache) Introduced August 18, 1997
Pentium II
- Introduced May 7, 1997
- Pentium Pro with MMX and improved 16-bit performance
- 242-pin Slot 1 (SEC) processor package
- Number of transistors 7.5 million
- 32 KiB L1 cache
- 512 KiB ½ speed external L2 cache
- The only Pentium II that did not have the cache at ½ speed of the core was the Pentium II 450 PE.
- Klamath - 0.35 µm process technology (233, 266, 300 MHz)
- Deschutes - 0.25 µm process technology (333, 350, 400, 450 MHz)
- Introduced January 26, 1998
- 66 MHz system bus speed (333 MHz variant), 100 MHz system bus speed for all models after
- Family 6 model 5
- Variants
- 333 MHz Introduced January 26, 1998
- 350 MHz Introduced April 15, 1998
- 400 MHz Introduced April 15, 1998
- 450 MHz Introduced August 24, 1998
- 233 MHz (Mobile) Introduced April 2, 1998
- 266 MHz (Mobile) Introduced April 2, 1998
- 333 MHz Pentium II Overdrive processor for Socket 8 Introduced August 10, 1998; Engineering Sample Photo
- 300 MHz (Mobile) Introduced September 9, 1998
- 333 MHz (Mobile)
Celeron (Pentium II-based)
- Covington - 0.25 µm process technology
- Mendocino - 0.25 µm process technology
- Introduced August 24, 1998
- 242-pin Slot 1 SEPP (Single Edge Processor Package), Socket 370 PPGA package
- Number of transistors 19 million
- 66 MHz system bus speed
- 32 KiB L1 cache
- 128 KiB integrated cache
- Family 6 model 6
- Variants
- 300A MHz Introduced August 24, 1998
- 333 MHz Introduced August 24, 1998
- 366 MHz Introduced January 4, 1999
- 400 MHz Introduced January 4, 1999
- 433 MHz Introduced March 22, 1999
- 466 MHz
- 500 MHz Introduced August 2, 1999
- 533 MHz Introduced January 4, 2000
- 266 MHz (Mobile)
- 300 MHz (Mobile)
- 333 MHz (Mobile) Introduced April 5, 1999
- 366 MHz (Mobile)
- 400 MHz (Mobile)
- 433 MHz (Mobile)
- 450 MHz (Mobile) Introduced February 14, 2000
- 466 MHz (Mobile)
- 500 MHz (Mobile) Introduced February 14, 2000
Pentium II Xeon (chronological entry)
- Introduced June 29, 1998
- See main entry
Pentium III
- Katmai - 0.25 µm process technology
- Introduced February 26, 1999
- Improved PII, i.e. P6-based core, now including Streaming SIMD Extensions (SSE)
- Number of transistors 9.5 million
- 512 KiB ½ speed L2 External cache
- 242-pin Slot 1 SECC2 (Single Edge Contact cartridge 2) processor package
- System Bus Speed 100 MHz, 133 MHz (B-models)
- Family 6 model 7
- Variants
- 450 MHz Introduced February 26, 1999
- 500 MHz Introduced February 26, 1999
- 550 MHz Introduced May 17, 1999
- 600 MHz Introduced August 2, 1999
- 533 MHz Introduced (133 MHz bus speed) September 27, 1999
- 600 MHz Introduced (133 MHz bus speed) September 27, 1999
- Coppermine - 0.18 µm process technology
- Introduced October 25, 1999
- Number of transistors 28.1 million
- 256 KiB Advanced Transfer L2 Cache (Integrated)
- 242-pin Slot-1 SECC2 (Single Edge Contact cartridge 2) processor package, 370-pin FC-PGA (Flip-chip pin grid array) package
- System Bus Speed 100 MHz (E-models), 133 MHz (EB models)
- Family 6 model 8
- Variants
- 500 MHz (100 MHz bus speed)
- 533 MHz
- 550 MHz (100 MHz bus speed)
- 600 MHz
- 600 MHz (100 MHz bus speed)
- 650 MHz (100 MHz bus speed) Introduced October 25, 1999
- 667 MHz Introduced October 25, 1999
- 700 MHz (100 MHz bus speed) Introduced October 25, 1999
- 733 MHz Introduced October 25, 1999
- 750 MHz (100 MHz bus speed) Introduced December 20, 1999
- 800 MHz (100 MHz bus speed) Introduced December 20, 1999
- 800 MHz Introduced December 20, 1999
- 850 MHz (100 MHz bus speed) Introduced March 20, 2000
- 866 MHz Introduced March 20, 2000
- 933 MHz Introduced May 24, 2000
- 1000 MHz Introduced March 8, 2000 (Not widely available at time of release)
- 1100 MHz
- 1133 MHz (first version recalled, later re-released)
- 400 MHz (Mobile) Introduced October 25, 1999
- 450 MHz (Mobile) Introduced October 25, 1999
- 500 MHz (Mobile) Introduced October 25, 1999
- 600 MHz (Mobile) Introduced January 18, 2000
- 650 MHz (Mobile) Introduced January 18, 2000
- 700 MHz (Mobile) Introduced April 24, 2000
- 750 MHz (Mobile) Introduced June 19, 2000
- 800 MHz (Mobile) Introduced September 25, 2000
- 850 MHz (Mobile) Introduced September 25, 2000
- 900 MHz (Mobile) Introduced March 19, 2001
- 1000 MHz (Mobile) Introduced March 19, 2001
- Tualatin - 0.13 µm process technology
- Introduced July 2001
- Number of transistors 28.1 million
- 32 KiB L1 cache
- 256 KiB or 512 KiB Advanced Transfer L2 cache (Integrated)
- 370-pin FC-PGA (Flip-chip pin grid array) package
- 133 MHz system bus speed
- Family 6 model 11
- Variants
- 1133 MHz (512 KiB L2)
- 1200 MHz
- 1266 MHz (512 KiB L2)
- 1333 MHz
- 1400 MHz (512 KiB L2)
Pentium II and III Xeon
- PII Xeon
- PIII Xeon
- Introduced October 25, 1999
- Number of transistors: 9.5 million at 0.25 µm or 28 million at 0.18 µm)
- L2 cache is 256 KiB, 1 MiB, or 2 MiB Advanced Transfer Cache (Integrated)
- Processor Package Style is Single Edge Contact Cartridge (S.E.C.C.2) or SC330
- System Bus Speed 133 MHz (256 KiB L2 cache) or 100 MHz (1 - 2 MiB L2 cache)
- System Bus Width 64 bit
- Addressable memory 64 gigabytes
- Used in two-way servers and workstations (256 KiB L2) or 4- and 8-way servers (1 - 2 MiB L2)
- Family 6 model 10
- Variants
- 500 MHz (0.25 µm process) Introduced March 17, 1999
- 550 MHz (0.25 µm process) Introduced August 23, 1999
- 600 MHz (0.18 µm process, 256 KiB L2 cache) Introduced October 25, 1999
- 667 MHz (0.18 µm process, 256 KiB L2 cache) Introduced October 25, 1999
- 733 MHz (0.18 µm process, 256 KiB L2 cache) Introduced October 25, 1999
- 800 MHz (0.18 µm process, 256 KiB L2 cache) Introduced January 12, 2000
- 866 MHz (0.18 µm process, 256 KiB L2 cache) Introduced April 10, 2000
- 933 MHz (0.18 µm process, 256 KiB L2 cache)
- 1000 MHz (0.18 µm process, 256 KiB L2 cache) Introduced August 22, 2000
- 700 MHz (0.18 µm process, 1 - 2 MiB L2 cache) Introduced May 22, 2000
Celeron (Pentium III Coppermine-based)
- Coppermine-128 - 0.18 µm process technology
- Introduced March,2000
- Streaming SIMD Extensions (SSE)
- Socket 370 PPGA processor package
- Number of transistors 28.1 million
- 66 MHz system bus speed, 100 MHz system bus speed on January 3, 2001
- 32 KiB L1 cache
- 128 KiB Advanced Transfer L2 cache
- Family 6 model 8
- Variants
- 533 MHz
- 566 MHz
- 633 MHz Introduced June 26, 2000
- 667 MHz Introduced June 26, 2000
- 700 MHz Introduced June 26, 2000
- 733 MHz Introduced November 13, 2000
- 766 MHz Introduced November 13, 2000
- 800 MHz
- 850 MHz Introduced April 9, 2001
- 900 MHz Introduced July 2, 2001
- 950 MHz Introduced August 31, 2001
- 1000 MHz Introduced August 31, 2001
- 1100 MHz Introduced August 31, 2001
- 1200 MHz Introduced October 2, 2001
- 1300 MHz Introduced January 3, 2002
- 550 MHz (Mobile)
- 600 MHz (Mobile) Introduced June 19, 2000
- 650 MHz (Mobile) Introduced June 19, 2000
- 700 MHz (Mobile) Introduced September 25, 2000
- 750 MHz (Mobile) Introduced March 19, 2001
- 800 MHz (Mobile)
- 850 MHz (Mobile) Introduced July 2, 2001
- 600 MHz (LV Mobile)
- 500 MHz (ULV Mobile) Introduced January 30, 2001
- 600 MHz (ULV Mobile)
XScale (chronological entry)
- Introduced August 23, 2000
- See main entry
Pentium 4 (not 4EE, 4E, 4F), Itanium, P4-based Xeon, Itanium 2 (chronological entries)
- Introduced April 2000 – July 2002
- See main entries
Celeron (Pentium III Tualatin-based)
- Tualatin Celeron - 0.13 µm process technology
- 32 KiB L1 cache
- 256 KiB Advanced Transfer L2 cache
- 100 MHz system bus speed
- Family 6 model 11
- Variants
- 1.0 GHz
- 1.1 GHz
- 1.2 GHz
- 1.3 GHz
- 1.4 GHz
Pentium M
- Banias 0.13 µm process technology
- Introduced March 2003
- 64 KiB L1 cache
- 1 MiB L2 cache (integrated)
- Based on Pentium III core, with SSE2 SIMD instructions and deeper pipeline
- Number of transistors 77 million
- Micro-FCPGA, Micro-FCBGA processor package
- Heart of the Intel mobile "Centrino" system
- 400 MHz Netburst-style system bus
- Family 6 model 9
- Variants
- 900 MHz (Ultra low voltage)
- 1.0 GHz (Ultra low voltage)
- 1.1 GHz (Low voltage)
- 1.2 GHz (Low voltage)
- 1.3 GHz
- 1.4 GHz
- 1.5 GHz
- 1.6 GHz
- 1.7 GHz
- Dothan 0.09 µm (90 nm) process technology
- Introduced May 2004
- 2 MiB L2 cache
- Revised data prefetch unit
- 533 MHz Netburst-style system bus
- Variants
- 1.0 GHz (Ultra low voltage)
- 1.1 GHz (Ultra low voltage)
- 1.2 GHz (Ultra low voltage)
- 1.3 GHz (Ultra low voltage)
- 1.3 GHz (Low voltage)
- 1.4 GHz (Low voltage)
- 1.5 GHz
- 1.6 GHz
- 1.7 GHz
- 1.8 GHz
- 1.9 GHz
- 2.0 GHz
- 2.13 GHz
- 2.26 GHz
Celeron M
- Banias-512 0.13 µm process technology
- Dothan-1024 90 nm process technology
- 64 KiB L1 cache
- 1 MiB L2 cache (integrated)
- SSE2 SIMD instructions
- No SpeedStep technology, is not part of the 'Centrino' package
- Variants
- 350 - 1.30 GHz
- 350J - 1.30 GHz, with Execute Disable bit
- 360 - 1.40 GHz
- 360J - 1.40 GHz, with Execute Disable bit
- 370 - 1.50 GHz, with Execute Disable bit
- 380 - 1.60 GHz, with Execute Disable bit
- 390 - 1.70 GHz, with Execute Disable bit
Intel Core
- Yonah 0.065 µm (65 nm) process technology
- Introduced January 2006
- 667 MHz frontside bus
- 2 MiB (Shared on Duo) L2 cache
- SSE3 SIMD instructions
- Variants:
- Intel Core Duo T2700 2.33 GHz
- Intel Core Duo T2600 2.16 GHz
- Intel Core Duo T2500 2.00 GHz
- Intel Core Duo T2400 1.83 GHz
- Intel Core Duo T2300 1.66 GHz
- Intel Core Solo T1300 1.66 GHz
- Intel Core Solo T1200 1.50 GHz
Dual-Core Xeon LV
- Sossaman 0.065 µm (65 nm) process technology
- Introduced March 2006
- Based on Yonah core, with SSE3 SIMD instructions
- 667 MHz frontside bus
- 2 MiB Shared L2 cache
- Variants
- 2.0 GHz
32-bit processors: NetBurst microarchitecture
Pentium 4
- 0.18 µm process technology (1.40 and 1.50 GHz)
- Introduced November 20, 2000
- L2 cache was 256 KiB Advanced Transfer Cache (Integrated)
- Processor Package Style was PGA423, PGA478
- System Bus Speed 400 MHz
- SSE2 SIMD Extensions
- Number of Transistors 42 million
- Used in desktops and entry-level workstations
- 0.18 µm process technology (1.7 GHz)
- 0.18 µm process technology (1.6 and 1.8 GHz)
- 0.18 µm process technology Willamette (1.9 and 2.0 GHz)
- Family 15 model 1
- Pentium 4 (2 GHz, 2.20 GHz)
- Pentium 4 (2.4 GHz)
- 0.13 µm process technology Northwood A (1.7, 1.8, 1.9, 2, 2.2, 2.4, 2.5, 2.6 GHz)
- Improved branch prediction and other microcodes tweaks
- 512 KiB integrated L2 cache
- Number of transistors 55 million
- 400 MHz system bus.
- Family 15 model 2
- 0.13 µm process technology Northwood B (2.26, 2.4, 2.53, 2.66, 2.8, 3.06 GHz)
- 533 MHz system bus. (3.06 includes Intel's hyper threading technology).
- 0.13 µm process technology Northwood C (2.4, 2.6, 2.8, 3.0, 3.2, 3.4 GHz)
- 800 MHz system bus (all versions include Hyper Threading)
- 6500 to 10000 MIPS
Itanium (chronological entry)
- Introduced 2001
- See main entry
Xeon
- Official designation now Xeon, i.e. not "Pentium 4 Xeon"
- Xeon 1.4, 1.5, 1.7 GHz
- Introduced May 21, 2001
- L2 cache was 256 KiB Advanced Transfer Cache (Integrated)
- Processor Package Style was Organic Lan Grid Array 603 (OLGA 603)
- System Bus Speed 400 MHz
- SSE2 SIMD Extensions
- Used in high-performance and mid-range dual processor enabled workstations
- Xeon 2.0 GHz and up to 3.6 GHz
- Introduced September 25, 2001
Itanium 2 (chronological entry)
- Introduced July 2002
- See main entry
Mobile Pentium 4-M
- 0.13 µm process technology
- 55 million transistors
- cache L2 512 KiB
- BUS a 400 MHz
- Supports up to 1 GB of DDR 266 MHz Memory
- Supports ACPI 2.0 and APM 1.2 System Power Management
- 1.3 V - 1.2 V (SpeedStep)
- Power: 1.2 GHz 20.8 W, 1.6 GHz 30 W, 2.6 GHz 35 W
- Sleep Power 5 W (1.2 V)
- Deeper Sleep Power = 2.9 W (1.0 V)
- 1.40 GHz - 23 April 2002
- 1.50 GHz - 23 April 2002
- 1.60 GHz - 4 March 2002
- 1.70 GHz - 4 March 2002
- 1.80 GHz - 23 April 2002
- 1.90 GHz - 24 June 2002
- 2.00 GHz - 24 June 2002
- 2.20 GHz - 16 September 2002
- 2.40 GHz - 14 January 2003
- 2.40 GHz - 14 January 2003
- 2.50 GHz - 16 April 2003
- 2.60 GHz - 11 June 2003
Pentium 4 EE
- Introduced September 2003
- EE = "Extreme Edition"
- Built from the Xeon's "Gallatin" core, but with 2MiB cache
Pentium 4E
- Introduced February 2004
- built on 0.09 µm (90 nm) process technology Prescott (2.4A, 2.8, 2.8A, 3.0, 3.2, 3.4, 3.6, 3.8) 1 MiB L2 cache
- 533 MHz system bus (2.4A and 2.8A only)
- Number of Transistors 125 million on 1MB Models
- Number of Transistors 169 million on 2MB Models
- 800 MHz system bus (all other models)
- Hyper-Threading support is only available on CPUs using the 800 MHz system bus.
- The processor's integer instruction pipeline has been increased from 20 stages to 31 stages, which theoretically allows for even greater clock speeds.
- 7500 to 11000 MIPS
- LGA-775 versions are in the 5xx series (32-bit) and 5x1 series (with EM64T)
- The 6xx series has 2 MiB L2 cache and EM64T
Pentium 4F
- Introduced Spring 2004
- same core as 4E, "Prescott"
- 3.2–3.6 GHz
- starting with the D0 stepping of this processor, EM64T 64-bit extensions has also been incorporated
64-bit processors: IA-64
- New instruction set, not at all related to x86.
- Current IA-64 processors support 32-bit x86 in hardware, but slowly.
Itanium
Itanium 2
- Released July 2002
- 900 MHz and 1 GHz
Pentium M (chronological entry)
- Introduced March 2003
- See main entry
Pentium 4EE, 4E (chronological entries)
- Introduced September 2003, February 2004, respectively
- See main entries
64-bit processors: EM64T - NetBurst
- Intel® Extended Memory 64 Technology
- Introduced Spring 2004, with the Pentium 4F (D0 and later P4 steppings)
- 64-bit architecture extension for the x86 range; near clone of AMD64
Pentium 4F, D0 and later steppings
- Starting with the D0 stepping of this processor, EM64T 64-bit extensions are supported
Pentium D
Main article: List of Intel Pentium D microprocessors- Dual-core microprocessor
- No Hyper-Threading
- 800(4x200) MHz front side bus
- Smithfield 90 nm process technology (2.8–3.4 GHz)
- Introduced May 26 2005
- 2.8–3.4 GHz (model numbers 820-840)
- Number of Transistors 230 million
- 1 MiB x 2 (non-shared, 2 MiB total) L2 cache
- Cache coherency between cores requires communication over the FSB
- Performance increase of 60% over similarly clocked Prescott
- 2.66 GHz (533 MHz FSB) Pentium D 805 introduced December 2005
- Presler 65 nm process technology (2.8–3.6 GHz)
- Introduced January 16 2006
- 2.8–3.6 GHz (model numbers 920-960)
- Number of Transistors 376 million
- 2 MiB x 2 (non-shared, 4 MiB total) L2 cache
Pentium Extreme Edition
- Dual-core microprocessor
- Enabled Hyper-Threading
- 1066(4x266) MHz front side bus
- Smithfield 90 nm process technology (3.2 GHz)
- Variants
- Pentium 840 EE - 3.20 GHz (2 x 1 MiB L2)
- Variants
- Presler 65 nm process technology (3.46, 3.73)
- 2 MiB x 2 (non-shared, 4 MiB total) L2 cache
- Variants
- Pentium 955 EE - 3.46 GHz
- Pentium 965 EE - 3.73 GHz
Xeon
- Nocona
- Introduced 2004
- Irwindale
- Introduced 2004
- Paxville DP (2.8 GHz)
- Introduced October 10, 2005
- Dual-core version of Irwindale, with 4 MiB of L2 Cache (2 MiB per core)
- 2.8 GHz
- 800 MT/s front side bus
- Paxville MP - 90 nm process (2.67 - 3.0 GHz)
- Introduced November 1, 2005
- Dual-Core Xeon 7000 series
- MP-capable version of Paxville DP
- 2 MiB of L2 Cache (1 MiB per core) or 4 MiB of L2 (2 MiB per core)
- 667 MT/s FSB or 800 MT/s FSB
- Dempsey - 65 nm process (2.67 - 3.73 GHz)
64-bit processors: EM64T - Intel Core Microarchitecture
Xeon
- Woodcrest - 65 nm process technology
- Server and Workstation CPU (SMP support for dual CPU system)
- Introduced June 26 2006
- Dual-Core
- Intel Virtualization Technology, multiple OS support
- EIST (Enhanced Intel SpeedStep Technology) in 5140, 5148LV, 5150, 5160
- Execute Disable Bit
- LaGrande Technology, enhanced security hardware extensions
- SSSE3 SIMD instructions
- iAMT2 (Intel Active Management Technology), remotely manage computers
- Variants
- Xeon 5160 - 3.00 GHz (4 MiB L2, 1333 MHz FSB, 80W)
- Xeon 5150 - 2.66 GHz (4 MiB L2, 1333 MHz FSB, 65W)
- Xeon 5140 - 2.33 GHz (4 MiB L2, 1333 MHz FSB, 65W)
- Xeon 5130 - 2.00 GHz (4 MiB L2, 1333 MHz FSB, 65W)
- Xeon 5120 - 1.86 GHz (4 MiB L2, 1066 MHz FSB, 65W)
- Xeon 5110 - 1.60 GHz (4 MiB L2, 1066 MHz FSB, 65W)
- Xeon 5148LV - 2.33 GHz (4 MiB L2, 1333 MHz FSB, 40W) -- Low Voltage Edition
Intel Core 2
- Conroe - 65 nm process technology
- Desktop CPU (no SMP support)
- Introduced July 27, 2006
- SSSE3 SIMD instructions
- Number of Transistors 291 Million on 4MB Models
- Number of Transistors 167 Million on 2MB Models
- Intel Virtualization Technology, multiple OS support
- LaGrande Technology, enhanced security hardware extensions
- Execute Disable Bit
- EIST (Enhanced Intel SpeedStep Technology)
- iAMT2 (Intel Active Management Technology), remotely manage computers
- LGA775
- Variants
- Core 2 Duo E6700 - 2.67 GHz (4 MiB L2, 1066 MHz FSB)
- Core 2 Duo E6600 - 2.40 GHz (4 MiB L2, 1066 MHz FSB)
- Core 2 Duo E6400 - 2.13 GHz (2 MiB L2, 1066 MHz FSB)
- Core 2 Duo E6300 - 1.86 GHz (2 MiB L2, 1066 MHz FSB)
- Core 2 Duo E4200 - 1.60 GHz (2 MiB L2, 800 MHz FSB)
- Conroe XE - 65 nm process technology
- Merom - 65 nm process technology
- Mobile CPU (no SMP support)
- Introduced July 27, 2006
- same features as Conroe
- Socket 479
- Variants
- Core 2 Duo T7600 - 2.33 GHz (4 MiB L2, 667 MHz FSB)
- Core 2 Duo T7400 - 2.16 GHz (4 MiB L2, 667 MHz FSB)
- Core 2 Duo T7200 - 2.00 GHz (4 MiB L2, 667 MHz FSB)
- Core 2 Duo T5600 - 1.83 GHz (2 MiB L2, 667 MHz FSB)
- Core 2 Duo T5500 - 1.66 GHz (2 MiB L2, 667 MHz FSB)
Detailed x86-µP release lists
- List of Intel Pentium 4 microprocessors
- List of Intel Pentium D microprocessors
- List of Intel Xeon microprocessors
- List of Intel Pentium M microprocessors
- List of Intel Core microprocessors
- List of Intel Core 2 microprocessors
- List of Intel Celeron microprocessors
See also
- List of Intel microcontrollers
- List of AMD microprocessors
- List of Motorola/Freescale microprocessors
- Intel P6
- NetBurst
- Intel Core Microarchitecture
References
- Not listed as an official model by Intel but used by Apple in their Intel-based Mac Mini, released March 2006)
External links
- The ChipList – By Adrian Offerman
- Intel Museum: History of the Microprocessor
- CPU decoder ring – The Tech Report
- Current Intel CPUs – The PC Doctor
- endian.net – Chip Roadmaps
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