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"offset within page" does not come from the page-table entry

The phrase should surely be . — Preceding unsigned comment added by 83.218.4.174 (talk) 23:56, 12 October 2016 (UTC)

You are of course correct - and nice catch, that's been on the page for a long time. You can of course make the change yourself if you want. Be WP:BOLD ! Jeh (talk) 03:08, 13 October 2016 (UTC)

"Paging and Virtual Memory"

Anyone reading this article should have at least a basic understanding of the concept of virtual memory in my opinion. And perhaps more importantly, the added section still requires such an understanding, because it provides no explanation of what paging and pages are to other readers. Therefore I don't see it as an improvement. It also seems to be copied and pasted from the source (judging from the excessive line breaks) and therefore not allowed.--Jasper Deng (talk) 19:40, 10 April 2017 (UTC)

It also didn't " how PAE works in IA-32" - the only thing it said about PAE is that "IA-32 architecture’s paging mechanism includes extensions that support Physical Address Extensions (PAE) to address physical address space greater than 4 GBytes." That says what PAE does, but doesn't say how it does it. The article already says what it does (in the lede, it says " It defines a page table hierarchy of three levels, with table entries of 64 bits each instead of 32, allowing these CPUs to access a physical address space larger than 4 gigabytes (2 bytes)."), and it later says how it does it (a quick mention in "Design", and a long description in "Page table structures"). Guy Harris (talk) 19:55, 10 April 2017 (UTC)

I'm glad I'm not the only one. I couldn't see where it "explained how PAE works" at all.

Worse: As suspected by Jasper Deng, the disputed material is a direct copy from volume 1, section 3.3.2, of the Intel® 64 and IA-32 Architectures Software Developer’s Manual. There is no doubt or ambiguity about that. The editor even copied the bulleted list from the Intel book as if it was ordinary text, resulting in "inline bullets". I have left a copyvio warning on their talk page.

What is especially odd here is that the same editor, PastieFace (talk · contribs · deleted contribs · logs · filter log · block user · block log), had previously dropped what was basically a CN tag on 3 GB barrier, claiming that a cited reference referred only to the Pentium Pro and that any statements about later processors were CN. Yet this editor is clearly aware of this Intel reference which defines PAE as part of the IA-32 architecture, not specific to any processor.

Both of these articles have been the target of much harassment over the last few years. I note that these recent instances happened shortly after I got a visit from our old friend and long-time sockpuppet Janagewen. Whether there's a connection there or not, I think PastieFace's future attempts can be ignored on WP:CIR grounds, and should be checked for WP:COPYVIO as well. Jeh (talk) 07:59, 11 April 2017 (UTC)

@PastieFace: If you bothered to look at the section on "Operating system support" you'll see that it's not a Windows-specific thing. And virtual memory has everything to do with it: each virtual address space remains 32-bit even if the physical memory is bigger, as your edit even mentions. If you do not have a good understanding of this concept, I suggest you avoid this topic.--Jasper Deng (talk) 20:28, 12 April 2017 (UTC)

Furthermore, if you don't have paging virtual memory enabled, PAE doesn't even exist - PAE involves a modified form of the page table, with larger page table entries capable of providing more bits of physical address, expanding the physical addresses generated for virtual addresses from 32 bits to 36 bits. Guy Harris (talk) 20:45, 12 April 2017 (UTC)

And wider on x64 processors while in long mode. Jeh (talk) 21:11, 12 April 2017 (UTC)

Further²more: PF claims PAE is Intel-only. That is wrong. PAE has been supported by AMD CPUs since the Athlon (K7) and continues in the K8, even when the latter is in legacy mode (ie running as an x86 CPU). It is true that AMD's support for PAE came several years later than Intel's: Intel had it in the Pentium Pro, late 1995, while AMD didn't have it until the Athlon, mid 1999.

So, yes, for a time, Intel supported PAE while AMD did not. But that time ended over 15 years ago!

I wish I could quote a K7-era AMD Architecture manual, but I can't find one. The oldest I have is the original hardcopy set for the AMD64 architecture, which does show that PAE is available on the K8 in legacy mode, but that isn't definitive for the K7. The online sources I've found are more recent still, but one would hope that they would at least disabuse PF of the notion that AMD doesn't support PAE at all on any platform. (See AMD64 Architecture Programmer’s Manual, Volume 2: System Programming, section 5.2.3 for legacy mode. For long mode, see 5.3: "Because PAE is always enabled in long mode ..."

On the bright side, PastiF's mistaken ideas have suggested to me a new diagram that may eliminate misconceptions like " once a process hit the 4GB limit, IA-32 CPU would start paging in and out of RAM using internal registers., that's what PAE is." (from PastieFace's edit to my talk page) (No, the CPU does not do that, and that isn't what PAE is.) Jeh (talk) 21:11, 12 April 2017 (UTC)

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