| Revision as of 20:37, 22 February 2008 editDiscospinster (talk | contribs)Administrators464,288 editsm rm typo← Previous edit | Revision as of 10:37, 30 March 2008 edit undoAnaxial (talk | contribs)Autopatrolled, Extended confirmed users, New page reviewers, Pending changes reviewers, Rollbackers66,632 editsm Wikified as part of the Wikification driveNext edit → | ||
| Line 1: | Line 1: | ||
| {{mergeto|Standard cell|Talk:Standard cell#Proposed_merge_from_Library_.28electronics.29|date=October 2007}} | {{mergeto|Standard cell|Talk:Standard cell#Proposed_merge_from_Library_.28electronics.29|date=October 2007}} | ||
| {{Wikify|date=April 2007}} | |||
| In ] design, '''library''' often refers to a collection of cells, |
In ] design, '''library''' often refers to a collection of cells, ]s or functional units that perform common operations and are used to build more complex ]s. | ||
| ==Standard cell libraries== | |||
| ⚫ | A |
||
| ⚫ | A ] library is a collection of low level ]s such as AND, OR, INVERT, flip-flops, latches and buffers. These cells are realized as fixed height, variable width full custom cells. The key aspect with these libraries is that they are of a fixed height, which enables them to be placed in rows, easing the process of automated digital layout. The cells are typically optimised full custom layouts, which minimise delays and area. | ||
| A typical standard cell library contains two main components: | A typical standard cell library contains two main components: | ||
| #Timing Abstract |
# Timing Abstract - This is generally in the ] Liberty format, and provides functional definitions, timing, power and noise information for each cell. | ||
| #Layout Abstract |
# Layout Abstract - Common formats that are in use are the Cadence LEF format, and the Synopsys Milkyway format, which contain reduced information about the cell layouts, sufficient for automated "Place and Route" tools. | ||
| They also may contain the following additional components: | They also may contain the following additional components: | ||
| * A full layout of the cells | |||
| * ]s of the cells | |||
| * ] models or ] models | |||
| * ] models | |||
| * ] rule decks | |||
| ⚫ | An example is a simple ] logic gate, which can be formed from OR, INVERT and AND gates. | ||
| ⚫ | There are many gates available in the electronics library; they are simply implemented in the circuit through ICs. Different ics are available for different logic gates and certain code words are defined for them. | ||
| ⚫ | Two logic which can be used to implement any logic gate are NAND and NOR gate. So this logic gates are called UNIVERSAL logic gates.<!-- I believe this is a relevant example. If someone can verify this, please feel free to remove this comment --> | ||
| ⚫ | An example is a simple XOR logic gate, which can be formed from OR, INVERT and AND gates. | ||
| ⚫ | There are many gates available in the electronics library they are simply implemented in the circuit through ICs |
||
| ⚫ | Two logic which can be used to implement any logic gate are NAND and NOR gate.So this logic gates are called UNIVERSAL logic gates.<!-- I believe this is a relevant example. If someone can verify this, please feel free to remove this comment --> | ||
| {{electronics-stub}} | {{electronics-stub}} | ||
Revision as of 10:37, 30 March 2008
 | It has been suggested that this article be merged into Standard cell and Talk:Standard cell#Proposed_merge_from_Library_.28electronics.29. (Discuss) Proposed since October 2007. |
In electronic design, library often refers to a collection of cells, macros or functional units that perform common operations and are used to build more complex logic blocks.
Standard cell libraries
A standard cell library is a collection of low level logic functions such as AND, OR, INVERT, flip-flops, latches and buffers. These cells are realized as fixed height, variable width full custom cells. The key aspect with these libraries is that they are of a fixed height, which enables them to be placed in rows, easing the process of automated digital layout. The cells are typically optimised full custom layouts, which minimise delays and area.
A typical standard cell library contains two main components:
- Timing Abstract - This is generally in the Synopsys Liberty format, and provides functional definitions, timing, power and noise information for each cell.
- Layout Abstract - Common formats that are in use are the Cadence LEF format, and the Synopsys Milkyway format, which contain reduced information about the cell layouts, sufficient for automated "Place and Route" tools.
They also may contain the following additional components:
- A full layout of the cells
- Spice models of the cells
- Verilog models or VHDL Vital models
- Parasitic extraction models
- DRC rule decks
An example is a simple XOR logic gate, which can be formed from OR, INVERT and AND gates.
There are many gates available in the electronics library; they are simply implemented in the circuit through ICs. Different ics are available for different logic gates and certain code words are defined for them.
Two logic which can be used to implement any logic gate are NAND and NOR gate. So this logic gates are called UNIVERSAL logic gates.
 | This electronics-related article is a stub. You can help Misplaced Pages by expanding it. |