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| * ] models or ] models | * ] models or ] models | ||
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| * ] rule decks | * ] rule decks | ||
| An example is a simple ] logic gate, which can be formed from OR, INVERT and AND gates. | An example is a simple ] logic gate, which can be formed from OR, INVERT and AND gates. | ||
Revision as of 03:15, 15 July 2008
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In electronic design, library often refers to a collection of cells, macros or functional units that perform common operations and are used to build more complex logic blocks.
Standard cell libraries
A standard cell library is a collection of low level logic functions such as AND, OR, INVERT, flip-flops, latches and buffers. These cells are realized as fixed height, variable width full custom cells. The key aspect with these libraries is that they are of a fixed height, which enables them to be placed in rows, easing the process of automated digital layout. The cells are typically optimised full custom layouts, which minimise delays and area.
A typical standard cell library contains two main components:
- Timing Abstract - This is generally in the Synopsys Liberty format, and provides functional definitions, timing, power and noise information for each cell.
- Layout Abstract - Common formats that are in use are the Cadence LEF format, and the Synopsys Milkyway format, which contain reduced information about the cell layouts, sufficient for automated "Place and Route" tools.
They also may contain the following additional components:
- A full layout of the cells
- Spice models of the cells
- Verilog models or VHDL Vital models
- Parasitic extraction models
- DRC rule decks
An example is a simple XOR logic gate, which can be formed from OR, INVERT and AND gates.
There are many gates available in the electronics library; they are simply implemented in the circuit through ICs. Different ics are available for different logic gates and certain code words are defined for them.
Two logic which can be used to implement any logic gate are NAND and NOR gate. So this logic gates are called UNIVERSAL logic gates.
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