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In semiconductor design, standard cell methodology is a method of designing Application Specific Integrated Circuits (ASICs) with mostly digital-logic features. Standard cell methodology is an example of design abstraction, whereby a low-level VLSI-layout is encapsulated into an abstract logic representation (such as a NAND gate). Cell-based methodology (the general class that standard-cell belongs to) makes it possible for one designer to focus on the high-level (logical function) aspect of digital-design, while another designer focused on the implementation (physical) aspect. Along with semiconductor manufacturing advances, standard cell methodology was responsible for allowing designers to scale ASICs from comparatively simple single-function ICs (of several thousand gates), to complex multi-million gate devices (SoC).

Construction of a standard cell

A standard cell is a group of transistor and interconnect structures, which provides a boolean logic function (e.g., AND, OR, XOR, XNOR, inverters) or a storage function (flipflop or latch). The simplest cells are direct representations of the elemental NAND, NOR, and XOR boolean function, although cells of much greater complexity are commonly used (such as a 2-bit full-adder, or muxed D-input flipflop.) The cell's boolean logic function is called its logical view: functional behavior is captured in the form of a truth table or Boolean algebra equation (for combinational logic), or a state transition table (for sequential logic).

Usually, the initial design of a standard cell is developed at the transistor level, in the form a transistor netlist. The netlist is a nodal description of transistors, of their connections to each other, and their terminals (ports) to the external environment. Designers use Computer Aided Design (CAD) programs such as SPICE to simulate the electronic behavior of the netlist, by declaring input stimulus (voltage or current waveforms) and then calculating the circuit's time domain (analogue) response. The simulations verify whether the netlist implements the requested function, and predict other pertinent parameters such as power consumption or signal propagation delay.

Since the logical and netlist views are only useful to abstract (algebraic) simulation, and not device fabrication, the physical representation of the standard cell must be designed too. Also called the layout view, this is the lowest level of design abstraction in common design practice. From a manufacturing perspective, the standard cell's VLSI layout is the most important view, as it is closest to an actual "manufacturing blueprint" of the standard cell. The layout is organized into base layers, which correspond to the different structures of the transistor devices, and interconnect lines, which join together the terminals of the transistor formations.

For a typical boolean function, many different transistor netlists exist that are functionally equivalent. Likewise, for a typical netlist, there exist many different layouts that fit the netlist's performance parameters. The designer's challenge is to minimize the manufacturing cost of the standard-cell's layout (generally by minimizing the circuit's die area), while still meeting the cell's speed and power performance requirements. Consequently, integrated circuit layout is a highly labor intensive job, despite the existence of design tools to aid this process.

Application of standard cell

Strictly speaking, a 2-input NAND or NOR function is sufficient to form any arbitrary boolean function set. But in modern ASIC design, standard cell methodology is practiced with a sizeable library (or libraries) of cells. The library usually contains multiple implementations of the same logic function, differing in area and speed. This variety enhances the efficiency of automated synthesis, place and route (SPR) tools. Indirectly, it also gives the designer greater freedom to perform implementation tradeoffs (area vs speed vs power consumption.) A complete group of standard cell descriptions is commonly called a technology library.

Commercially available Electronic Design Automation (EDA) tools use the technology libraries to automate synthesis, placement, and routing of a digital ASIC. The technology library is developed and distributed by the foundry operator. The library (along with a design netlist format) is the basis for exchanging design information between different phases of the SPR process.

Synthesis

Using the technology library's cell logical view, the Logic Synthesis tool performs the process of mathematically transforming the ASIC's register-transfer level (RTL) description into a technology-dependent netlist. This process is analogous to a software compiler converting a high-level C-program listing into a processor-dependent, assembly language listing.

The netlist is the standard cell representation of the ASIC design, at the logical view level. It consists of instances of the standard-cell library gates, and port-connectivity between gates. Proper synthesis techniques ensure mathematical equivalency between the synthesized netlist and original RTL description. The netlist contains no unmapped RTL statements and declarations.

The High Level Synthesis tool performs the process of transforming the C-level models (SystemC, ANSI C/C++) description into a technology-dependent netlist.

Placement

The placement tool starts the physical implementation of the ASIC. With a 2-D floorplan provided by the ASIC-designer, the placer tool assigns locations for each gate in the netlist. The resulting placed gates netlist contains the physical location of each of the netlist's standard-cells, but retains an abstract description of how the gates' terminals are wired to each other.

Typically the standard cells have a constant size in at least one dimension that allows them to be lined up in rows on the integrated circuit. The chip will consist of a huge number of rows (with power and ground running next to each row) with each row filled with the various cells making up the actual design. Placers obey certain rules: Each gate is assigned a unique (exclusive) location on the diemap. A given gate is placed once, and may not occupy or overlap the location of any other gate.

Routing

Using the placed gates netlist and the layout view of the library, the router adds both signal connect lines and power supply lines. The fully routed physical netlist contains the listing of gates from synthesis, the placement of each gate from placement, and the drawn interconnects from routing.

DRC/LVS

Design Rule Check (DRC) and Layout Versus Schematic (LVS) are verification processes. Reliable device fabrication at modern deep submicrometre (0.13 µm and below) requires strict observance of transistor spacing, metal layer thickness, and power density rules. DRC exhaustively compares the physical netlist against a set of "foundry design rules" (from the foundry operator), then flags any observed violations.

LVS is a process that confirms that the layout has the same structure as the associated schematic; this is typically the final step in the layout process. The LVS tool takes as an input a schematic diagram and the extracted view from a layout. It then generates a netlist from each one and compares them. Nodes, ports, and device sizing are all compared. If they are the same, LVS passes and the designer can continue. It should be noted that LVS tends to consider transistor fingers to be the same as an extra-wide transistor. Thus, 4 transistors in parallel (each 1 um wide), a 4-finger 1 um transistor, and a 4 um transistor would all be viewed as the same by the LVS tool. Functionality of .lib files will be taken from spice models and added as an attribute to the .lib file.

Other cell-based methodologies

Standard cell falls into a more general class of design automation flows called cell-based design. Structured ASICs, FPGAs, and CPLDs are variations on cell-based design. From the designer's standpoint, all share the same input frontend: an RTL description of the design. The three techniques, however, differ substantially in the details of the SPR flow and physical implementation.

Complexity measure

For digital standard cell designs, for instance in CMOS, a common technology-independent metric for complexity measure is gate equivalents (GE).

See also

• Integrated Circuits
• Circuit Design
• Semiconductor
• Very-large-scale integration (VLSI)

External links

• VLSI Technology— This site contains support material for a book that Graham Petley is writing, The Art of Standard Cell Library Design
• Asic Service - overview of Standard Cell as well as white papers.
• Oklahoma State University— This site contains support material for a complete System on Chip standard cell library that utilizes public-domain and Mentor Graphics/Synopsys/Cadence Design System tools
• Virginia Tech— This is a standard cell library developed by the Virginia Technology VLSI for Telecommunications (VTVT)
• ChipX - Interesting overview of Standard Cell as well as metal layer configurable chip options.

• Articles to be merged from October 2007
• Electronic design automation
• Logic gates