Revision as of 19:40, 10 April 2017 editJasper Deng (talk | contribs)Edit filter managers, Extended confirmed users, Pending changes reviewers, Rollbackers53,719 edits →"Paging and Virtual Memory": new section← Previous edit | Revision as of 19:55, 10 April 2017 edit undoGuy Harris (talk | contribs)Extended confirmed users76,458 edits →"Paging and Virtual Memory": And that section didn't do what the edit comment said the section did.Next edit → | ||
Line 25: | Line 25: | ||
Anyone reading this article should have at least a basic understanding of the concept of ] in my opinion. And perhaps more importantly, the added section ''still'' requires such an understanding, because it provides no explanation of what paging and pages are to other readers. Therefore I don't see it as an improvement. It also seems to be copied and pasted from the source (judging from the excessive line breaks) and therefore not allowed.--] ] 19:40, 10 April 2017 (UTC) | Anyone reading this article should have at least a basic understanding of the concept of ] in my opinion. And perhaps more importantly, the added section ''still'' requires such an understanding, because it provides no explanation of what paging and pages are to other readers. Therefore I don't see it as an improvement. It also seems to be copied and pasted from the source (judging from the excessive line breaks) and therefore not allowed.--] ] 19:40, 10 April 2017 (UTC) | ||
:It also didn't " how PAE works in IA-32" - the only thing it said about PAE is that "IA-32 architecture’s paging mechanism includes extensions that support Physical Address Extensions (PAE) to address physical address space greater than 4 GBytes." That says what PAE does, but doesn't say how it does it. The article ''already'' says what it does (in the lede, it says " It defines a ] hierarchy of three levels, with table entries of 64 bits each instead of 32, allowing these CPUs to access a physical ] larger than 4 ]s (2<sup>32</sup> bytes)."), ''and'' it later says how it does it (a quick mention in "Design", and a long description in "Page table structures"). ] (]) 19:55, 10 April 2017 (UTC) |
Revision as of 19:55, 10 April 2017
This is the talk page for discussing improvements to the Physical Address Extension article. This is not a forum for general discussion of the article's subject. |
|
Find sources: Google (books · news · scholar · free images · WP refs) · FENS · JSTOR · TWL |
This article has not yet been rated on Misplaced Pages's content assessment scale. It is of interest to the following WikiProjects: | ||||||||||||||||||||||||
Please add the quality rating to the {{WikiProject banner shell}} template instead of this project banner. See WP:PIQA for details.
{{WikiProject banner shell}} template instead of this project banner. See WP:PIQA for details.
|
Archives (Index) |
This page is archived by ClueBot III. |
"offset within page" does not come from the page-table entry
The phrase should surely be . — Preceding unsigned comment added by 83.218.4.174 (talk) 23:56, 12 October 2016 (UTC)
- You are of course correct - and nice catch, that's been on the page for a long time. You can of course make the change yourself if you want. Be WP:BOLD ! Jeh (talk) 03:08, 13 October 2016 (UTC)
"Paging and Virtual Memory"
Anyone reading this article should have at least a basic understanding of the concept of virtual memory in my opinion. And perhaps more importantly, the added section still requires such an understanding, because it provides no explanation of what paging and pages are to other readers. Therefore I don't see it as an improvement. It also seems to be copied and pasted from the source (judging from the excessive line breaks) and therefore not allowed.--Jasper Deng (talk) 19:40, 10 April 2017 (UTC)
- It also didn't " how PAE works in IA-32" - the only thing it said about PAE is that "IA-32 architecture’s paging mechanism includes extensions that support Physical Address Extensions (PAE) to address physical address space greater than 4 GBytes." That says what PAE does, but doesn't say how it does it. The article already says what it does (in the lede, it says " It defines a page table hierarchy of three levels, with table entries of 64 bits each instead of 32, allowing these CPUs to access a physical address space larger than 4 gigabytes (2 bytes)."), and it later says how it does it (a quick mention in "Design", and a long description in "Page table structures"). Guy Harris (talk) 19:55, 10 April 2017 (UTC)