Revision as of 23:25, 10 May 2020 editOnzite. (talk | contribs)12 edits →PAE Xeon only: new section← Previous edit | Revision as of 23:43, 10 May 2020 edit undoClueBot III (talk | contribs)Bots1,372,843 editsm Archiving 1 discussion to Talk:Physical Address Extension/Archives/2020/February. (BOT)Next edit → | ||
Line 16: | Line 16: | ||
}} | }} | ||
== As to the PAE kernel for Linux == | |||
That is a long and old news that even though the processors, x86 or IA-32, lack support of PAE, could also be equipped with PAE kernel. As to the further information, one could retrieve such information from Linux kernel source, from http://www.kernel.org. <!-- Template:Unsigned IP --><small class="autosigned">— Preceding ] comment added by ] (]) 00:42, 9 May 2017 (UTC)</small> <!--Autosigned by SineBot--> | |||
:The only kernels that can run on a processor without PAE support are 1) kernels without PAE support and 2) kernels that check whether the hardware supports PAE, enables it if and only if present, ''and'', depending on whether PAE is enabled or not, use different code to manage page table entries. | |||
:If you look at the Linux kernel source, in {{mono|arch/x86/include/asm/pgtable_32_types.h}}, you'll see a comment | |||
/* | |||
* The Linux x86 paging architecture is 'compile-time dual-mode', it | |||
* implements both the traditional 2-level x86 page tables and the | |||
* newer 3-level PAE-mode page tables. | |||
*/ | |||
:and, in fact, whether the kernel uses pre-PAE or PAE page tables on 32-bit x86 processors is set at compile time, ''not'' determined at run time, so a kernel with PAE support will work only on a machine that supports PAE; a kernel without PAE support will work on a machine that supports PAE, but it won't use PAE and will only handle 4GB of physical memory. | |||
:So, no, you can't run a PAE kernel on a processor that lacks PAE support; anybody who believes that it does either hasn't read the Linux kernel source or read it but didn't understand it. ] (]) 03:34, 9 May 2017 (UTC) | |||
:: yeah, you are definitely correct! <!-- Template:Unsigned IP --><small class="autosigned">— Preceding ] comment added by ] (]) 12:50, 9 May 2017 (UTC)</small> <!--Autosigned by SineBot--> | |||
{{Done}} | |||
== 32 bit Windows specific == | == 32 bit Windows specific == |
Revision as of 23:43, 10 May 2020
This is the talk page for discussing improvements to the Physical Address Extension article. This is not a forum for general discussion of the article's subject. |
|
Find sources: Google (books · news · scholar · free images · WP refs) · FENS · JSTOR · TWL |
This article has not yet been rated on Misplaced Pages's content assessment scale. It is of interest to the following WikiProjects: | ||||||||||||||||||||||||
Please add the quality rating to the {{WikiProject banner shell}} template instead of this project banner. See WP:PIQA for details.
{{WikiProject banner shell}} template instead of this project banner. See WP:PIQA for details.
|
Archives (Index) |
This page is archived by ClueBot III. |
32 bit Windows specific
If the Microsoft Windows discussed is specific to 32 bit, then it would be more clearer to put them in the header. As many people who reads the page for quick reference may miss this detail.
Tsenapathy (talk) 17:40, 29 November 2018 (UTC)
- PAE is a processor feature. Information about support in specific OSs (Windows or otherwise) therefore does not belong in the article header. The processor feature would exist even if no OSs supported it. Jeh (talk) 17:59, 29 November 2018 (UTC)
PAE Xeon only
It should be made clear the only IA-32 processor which supported Physical Address Extension as defined by Intel was Xeon. PAE requires BOTH 36 address registers AND 36bit data bus for RAM.
All IA-32 processors had at most a 32bit data bus. 36 address registers only allows paging - it is not PAE support.
Only Xeon had 36bits for RAM. (2x 16bit banks + 4bit segment selector). (Xeon was technically a 36bit CPU).
Onzite. (talk) 23:25, 10 May 2020 (UTC)
Categories: