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Revision as of 23:43, 10 May 2020 editClueBot III (talk | contribs)Bots1,372,843 editsm Archiving 1 discussion to Talk:Physical Address Extension/Archives/2020/February. (BOT)← Previous edit Revision as of 23:44, 10 May 2020 edit undo122.61.41.43 (talk) PAE Xeon only: correction.Next edit →
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All IA-32 processors had at most a 32bit data bus. 36 address registers only allows paging - it is not PAE support. All IA-32 processors had at most a 32bit data bus. 36 address registers only allows paging - it is not PAE support.


Only Xeon had 36bits for RAM. (2x 16bit banks + 4bit segment selector). (Xeon was technically a 36bit CPU). Only Xeon had 36bits for RAM. Xeon supported 8GB RAM total. The 8GB was split into 2x 4GB memory banks accessed one bank at a time. The 32bit + 4bit bus allowed a segment selector.
(Xeon was technically a 36bit CPU).


] (]) 23:25, 10 May 2020 (UTC) ] (]) 23:25, 10 May 2020 (UTC)

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32 bit Windows specific

If the Microsoft Windows discussed is specific to 32 bit, then it would be more clearer to put them in the header. As many people who reads the page for quick reference may miss this detail.

Tsenapathy (talk) 17:40, 29 November 2018 (UTC)

PAE is a processor feature. Information about support in specific OSs (Windows or otherwise) therefore does not belong in the article header. The processor feature would exist even if no OSs supported it. Jeh (talk) 17:59, 29 November 2018 (UTC)

PAE Xeon only

It should be made clear the only IA-32 processor which supported Physical Address Extension as defined by Intel was Xeon. PAE requires BOTH 36 address registers AND 36bit data bus for RAM.

All IA-32 processors had at most a 32bit data bus. 36 address registers only allows paging - it is not PAE support.

Only Xeon had 36bits for RAM. Xeon supported 8GB RAM total. The 8GB was split into 2x 4GB memory banks accessed one bank at a time. The 32bit + 4bit bus allowed a segment selector. (Xeon was technically a 36bit CPU).

Onzite. (talk) 23:25, 10 May 2020 (UTC)

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