The following pages link to Speculative execution
External toolsShowing 50 items.
View (previous 50 | next 50) (20 | 50 | 100 | 250 | 500)- Application-specific integrated circuit (links | edit)
- 64-bit computing (links | edit)
- Hyper-threading (links | edit)
- One-instruction set computer (links | edit)
- Z3 (computer) (links | edit)
- Digital signal processor (links | edit)
- Multiple instruction, multiple data (links | edit)
- Pentium Pro (links | edit)
- Memory management unit (links | edit)
- Apollo Guidance Computer (links | edit)
- IAS machine (links | edit)
- Predication (computer architecture) (links | edit)
- Instructions per cycle (links | edit)
- Instruction pipelining (links | edit)
- Program optimization (links | edit)
- Clock rate (links | edit)
- X86-64 (links | edit)
- Instruction-level parallelism (links | edit)
- Power management (links | edit)
- Stack (abstract data type) (links | edit)
- Barrel shifter (links | edit)
- Simultaneous multithreading (links | edit)
- Memory-mapped I/O and port-mapped I/O (links | edit)
- Back-side bus (links | edit)
- Mobile processor (links | edit)
- Coprocessor (links | edit)
- Index register (links | edit)
- Re-order buffer (links | edit)
- Hazard (computer architecture) (links | edit)
- Classic RISC pipeline (links | edit)
- Branch predictor (links | edit)
- Execution (computing) (links | edit)
- Adder (electronics) (links | edit)
- Register renaming (links | edit)
- Prefetch input queue (links | edit)
- Von Neumann architecture (links | edit)
- Timing attack (links | edit)
- Processor register (links | edit)
- DEC PRISM (links | edit)
- 4-bit computing (links | edit)
- Translation lookaside buffer (links | edit)
- Instruction cycle (links | edit)
- Status register (links | edit)
- X86 instruction listings (links | edit)
- NX bit (links | edit)
- Speculative evaluation (redirect page) (links | edit)
- Explicitly parallel instruction computing (links | edit)
- Addressing mode (links | edit)
- CPU cache (links | edit)
- CORDIC (links | edit)