The following pages link to Universal Turing machine
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View (previous 50 | next 50) (20 | 50 | 100 | 250 | 500)- Simultaneous multithreading (links | edit)
- Speculative execution (links | edit)
- Horn clause (links | edit)
- Memory-mapped I/O and port-mapped I/O (links | edit)
- Back-side bus (links | edit)
- Many-one reduction (links | edit)
- Mobile processor (links | edit)
- Coprocessor (links | edit)
- Index register (links | edit)
- History of computing (links | edit)
- Graphics processing unit (links | edit)
- Hazard (computer architecture) (links | edit)
- Ray Solomonoff (links | edit)
- Algorithmic probability (links | edit)
- Computing Machinery and Intelligence (links | edit)
- Classic RISC pipeline (links | edit)
- Branch predictor (links | edit)
- Execution (computing) (links | edit)
- Adder (electronics) (links | edit)
- Register renaming (links | edit)
- Prefetch input queue (links | edit)
- UTM (links | edit)
- Von Neumann architecture (links | edit)
- Processor register (links | edit)
- DEC PRISM (links | edit)
- Register machine (links | edit)
- 4-bit computing (links | edit)
- Translation lookaside buffer (links | edit)
- Random-access machine (links | edit)
- Instruction cycle (links | edit)
- HP-41C (links | edit)
- NX bit (links | edit)
- Donald Davies (links | edit)
- Explicitly parallel instruction computing (links | edit)
- Raphael M. Robinson (links | edit)
- List of terms relating to algorithms and data structures (links | edit)
- Alternating Turing machine (links | edit)
- Addressing mode (links | edit)
- CPU cache (links | edit)
- CORDIC (links | edit)
- Temporal multithreading (links | edit)
- 36-bit computing (links | edit)
- Automatic Computing Engine (links | edit)
- Multiple instruction, single data (links | edit)
- Out-of-order execution (links | edit)
- Complex programmable logic device (links | edit)
- Single instruction, single data (links | edit)
- Glider (Conway's Game of Life) (links | edit)
- Memory buffer register (links | edit)
- Turing reduction (links | edit)