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The following pages link to Simultaneous and heterogeneous multithreading

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• Floating point operations per second (links | edit)
• System on a chip (links | edit)
• SuperH (links | edit)
• Microsequencer (links | edit)
• Parallel computing (links | edit)
• Application-specific integrated circuit (links | edit)
• 64-bit computing (links | edit)
• Parallel algorithm (links | edit)
• Hyper-threading (links | edit)
• One-instruction set computer (links | edit)
• Z3 (computer) (links | edit)
• Digital signal processor (links | edit)
• Multiple instruction, multiple data (links | edit)
• Semaphore (programming) (links | edit)
• Cache coherence (links | edit)
• Memory management unit (links | edit)
• Scalability (links | edit)
• Apollo Guidance Computer (links | edit)
• IAS machine (links | edit)
• Instructions per cycle (links | edit)
• Instruction pipelining (links | edit)
• Message Passing Interface (links | edit)
• Parallel Virtual Machine (links | edit)
• Flynn's taxonomy (links | edit)
• Clock rate (links | edit)
• Distributed memory (links | edit)
• Instruction-level parallelism (links | edit)
• Power management (links | edit)
• Consistency model (links | edit)
• Barrel shifter (links | edit)
• Simultaneous multithreading (links | edit)
• Speculative execution (links | edit)
• Memory-mapped I/O and port-mapped I/O (links | edit)
• Back-side bus (links | edit)
• Mobile processor (links | edit)
• Coprocessor (links | edit)
• OpenMP (links | edit)
• Index register (links | edit)
• Hazard (computer architecture) (links | edit)
• Memory coherence (links | edit)
• Distributed shared memory (links | edit)
• Classic RISC pipeline (links | edit)
• Branch predictor (links | edit)
• Application checkpointing (links | edit)
• Execution (computing) (links | edit)
• Adder (electronics) (links | edit)
• Register renaming (links | edit)
• Prefetch input queue (links | edit)
• Race condition (links | edit)
• Von Neumann architecture (links | edit)