Puma (microarchitecture) - Misplaced Pages

(Redirected from AMD Puma) Microarchitecture by AMD

Puma - Family 16h (2nd-gen)
General information
Launched	mid-2014
Discontinued	mid-2015
Common manufacturer	AMD
Performance
Max. CPU clock rate	1.35 GHz to 2.5 GHz
Cache
L1 cache	64 KB per core
L2 cache	1 MB to 2 MB shared
Architecture and classification
Technology node	28 nm
Instruction set	AMD64 (x86-64)
Physical specifications
Cores	2–4
GPUs	Radeon RX: 128 cores, 300–800 Mhz
Sockets	Socket AM1 Socket FT3b (BGA-769)
Products, models, variants
Core names	Beema Mullins
Brand name	AMD APU
History
Predecessor	Jaguar - Family 16h

This article is about the microarchitecture. For the 2008 mobile platform, see AMD mobile platform § Puma platform (2008).

The Puma Family 16h is a low-power microarchitecture by AMD for its APUs. It succeeds the Jaguar as a second-generation version, targets the same market, and belongs to the same AMD architecture Family 16h. The Beema line of processors are aimed at low-power notebooks, and Mullins are targeting the tablet sector.

Design

The Puma cores use the same microarchitecture as Jaguar, and inherits the design:

Out-of-order execution and Speculative execution, up to 4 CPU cores
Two-way integer execution
Two-way 128-bit wide floating-point and packed integer execution
Integer hardware divider
Puma does not feature clustered multi-thread (CMT), meaning that there are no "modules"
Puma does not feature Heterogeneous System Architecture or zero-copy
32 KiB instruction + 32 KiB data L1 cache per core
1–2 MiB unified L2 cache shared by two or four cores
Integrated single channel memory controller supporting 64bit DDR3L
3.1 mm area per core

Instruction set support

Like Jaguar, the Puma core has support for the following instruction sets and instructions: MMX, SSE, SSE2, SSE3, SSSE3, SSE4a, SSE4.1, SSE4.2, AVX, F16C, CLMUL, AES, BMI1, MOVBE (Move Big-Endian instruction), XSAVE/XSAVEOPT, ABM (POPCNT/LZCNT), and AMD-V.

Improvements over Jaguar

19% CPU core leakage reduction at 1.2V
38% GPU leakage reduction
500 mW reduction in memory controller power
200 mW reduction in display interface power
Chassis temperature aware turbo boost
Selective boosting according to application needs (intelligent boost)
Support for ARM TrustZone via integrated Cortex-A5 processor
Support for DDR3L-1866 memory

Puma+

AMD released a revision of the Puma microarchitecture, Puma+, which is integrated into the Carrizo-L APU platform.

Features

APU features table

Processors

Desktop/Mobile (Beema)

Family	Model	Socket	CPU				GPU			TDP (W)	DDR3L Memory Speed
Family	Model	Socket	Cores	Freq. (GHz)	Max. Turbo (GHz)	L2 Cache (MB)	Model	Config.	Max. Freq. (MHz)	TDP (W)	DDR3L Memory Speed
A8	6410	Socket FT3b	4	2.0	2.4	2	Radeon R5	128:?:?	800	15	1866
A6	6310			1.8	2.4		Radeon R4		800	15	1866
A4	6250J			2.0	—		Radeon R3		600	25	1600
A4	6210			1.8			Radeon R3		600	15
E2	6110			1.5			Radeon R2		500	15
E1	6010		2	1.35		1	Radeon R2		350	10	1333

Tablet (Mullins)

Family	Model	CPU				GPU			Power		DDR3L Memory Speed
Family	Model	Cores	Freq. (GHz)	Max. Turbo (GHz)	L2 Cache (MB)	Model	Config.	Max. Freq. (MHz)	TDP (W)	SDP (W)	DDR3L Memory Speed
A10 Micro	6700T	4	1.2	2.2	2	Radeon R6	128:?:?	500	4.5	2.8	1333
A6 Micro	6500T		1.2	1.8		Radeon R4		401
A4 Micro	6400T		1.0	1.6		Radeon R3		350
E1 Micro	6200T	2	1.0	1.4	1	Radeon R2		300	3.95		1066

References

^ "Software Optimization Guide for Family 16h Processors". AMD. Retrieved August 3, 2013.
"AMD launches new Beema, Mullins SoCs". ExtremeTech. 2014-04-29. Retrieved 2014-05-02.
Shimpi, Anand. "AMD Beema/Mullins Architecture & Performance Preview". AnandTech. Retrieved 29 April 2014.
Shimpi, Anand. "New Turbo Boost, The Lineup and Trustzone". AnandTech. Retrieved 29 April 2014.
Woligroski, Don (28 April 2014). "Meet The Mullins And Beema Tablet APUs". Toms Hardware. Retrieved 29 April 2014.

External links

AMD processors

Lists

Processors
- K5
- K6
- Athlon
  - XP
  - 64
  - X2
  - II
- Phenom
- FX
- Ryzen
- Duron
- Sempron
- Turion
- Opteron
- Epyc
APUs
Microarchitectures
Chipsets

Microarchitectures

IA-32 (32-bit)	K5 K6 Athlon/K7
x86-64 desktop	K8 K9 K10 (aka 10h) 15h Bulldozer Piledriver Steamroller Excavator Zen 1st gen Zen+ Zen 2 Zen 3 Zen 3+ Zen 4 Zen 5 Zen 6
x86-64 low-power	Bobcat (aka 14h) 16h Jaguar Puma
ARM64	K12 (aka 12h)

Current products

x86-64 (64-bit)	Athlon Ryzen Threadripper Epyc

Discontinued

Early x86 (16-bit)	Am286
IA-32 (32-bit)	Am386 Am486 Am5x86 K5 K6 K6-2 K6-III Athlon XP MP Duron Geode AMD Élan
x86-64 (64-bit)	Athlon 64 X2 II Sempron Turion Phenom II FX Opteron A-series APUs
Other	Am9080 Am2900 list Am29000 Alchemy MIPS32

Italics indicates an upcoming architecture.

AMD sockets and chipsets

AMD sockets

Desktop sockets	Super Socket 7 (1998) Slot A (1999) 939 (2004) 940 (2003) AM2 (2006) AM2+ (2007) AM3 (2009) AM3+ (2011) FM1 (2011) FM2 (2012) FM2+ (2014) AM1 (2014) AM4 (2016) TR4 (2017) sTRX4 (2019) sWRX8 (2020) AM5 (2022) sTR5 (2023)
Mobile sockets	563 S1 (2006) FT1 (2011) FP2 (2012) FS1 FT3 FP3 (2014) FP4 (2015) FT4 (2016) FP5 (2019) FT5 FP6 (2020) FP7 (2022) FP8 FL1 (2023)
Server sockets	940 F (2006) F+ G3 (not released) G34 C32 (2010) SP3 (2017) SP4 (2018) SP5 (2022) SP6 (2023)
Combined sockets	Socket A (2000) 754 (2003)

ATI / AMD chipsets

ATI chipsets	IGP 300 series/RX380 Radeon Xpress 200 CrossFire Xpress 3200 Radeon Xpress 1250
AMD chipsets	480X/570X/580X 690 Series 7-Series 8-Series 9-Series Fusion Controller Hubs AM4 chipsets TR4 chipsets sTRX4 chipsets sWRX8 chipsets AM5 chipsets sTR5 chipsets

Combined means that the given socket is supported by all platforms, including desktop, mobile, and server.

Single-board computer and single-board microcontroller

Devices

SoCs

ARM	Actions Allwinner Ax Apple M1 Exynos i.MX HiSiliconK3V3 MediaTek Nomadik NovaThor OMAP Rockchip Qualcomm Snapdragon Tegra WonderMedia
MIPS	Jz
x86/x86-64	AMD Élan Atom Jaguar-based Puma-based Quark

Software

Categories: