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This is a comparison of ARM instruction set architecture application processor cores designed by ARM Holdings (ARM Cortex-A) and 3rd parties. It does not include ARM Cortex-R, ARM Cortex-M, or legacy ARM cores.

ARMv7-A

This is a table comparing 32-bit central processing units that implement the ARMv7-A (A means Application) instruction set architecture and mandatory or optional extensions of it, the last AArch32.

This list is incomplete; you can help by adding missing items. (February 2014)
Core Decode
width
Execution
ports
Pipeline
depth
Out-of-order execution FPU Pipelined
VFP
FPU
registers
NEON
(SIMD)
big.LITTLE
role
Virtualization Process
technology
L0
cache
L1
cache
L2
cache
Core
configurations
Speed
per
core
(DMIPS
/ MHz
)
ARM part number
(in the main ID register)
ARM Cortex-A5 1 8 No VFPv4 (optional) 16 × 64-bit 64-bit wide (optional) No No 40/28 nm 4–64 KiB / core 1, 2, 4 1.57 0xC05
ARM Cortex-A7 2 5 8 No VFPv4 Yes 16 × 64-bit 64-bit wide LITTLE Yes 40/28 nm 8–64 KiB / core up to 1 MiB (optional) 1, 2, 4, 8 1.9 0xC07
ARM Cortex-A8 2 2 13 No VFPv3 No 32 × 64-bit 64-bit wide No No 65/55/45 nm 32 KiB + 32 KiB 256 or 512 (typical) KiB 1 2.0 0xC08
ARM Cortex-A9 2 3 8–11 Yes VFPv3 (optional) Yes (16 or 32) × 64-bit 64-bit wide (optional) Companion Core No 65/45/40/32/28 nm 32 KiB + 32 KiB 1 MiB 1, 2, 4 2.5 0xC09
ARM Cortex-A12 2 11 Yes VFPv4 Yes 32 × 64-bit 128-bit wide No Yes 28 nm 32–64 KiB + 32 KiB 256 KiB, to 8 MiB 1, 2, 4 3.0 0xC0D
ARM Cortex-A15 3 8 15/17-25 Yes VFPv4 Yes 32 × 64-bit 128-bit wide big Yes 32/28/20 nm 32 KiB + 32 KiB per core up to 4 MiB per cluster, up to 8 MiB per chip 2, 4, 8 (4×2) 3.5 to 4.01 0xC0F
ARM Cortex-A17 2 11+ Yes VFPv4 Yes 32 × 64-bit 128-bit wide big Yes 28 nm 32 KiB + 32 KiB per core 256 KiB, up to 8 MiB up to 4 4.0 0xC0E
Qualcomm Scorpion 2 3 10 Yes (FXU&LSU only) VFPv3 Yes 128-bit wide No 65/45 nm 32 KiB + 32 KiB 256 KiB (single-core)
512 KiB (dual-core)
1, 2 2.1 0x00F
Qualcomm Krait 3 7 11 Yes VFPv4 Yes 128-bit wide No 28 nm 4 KiB + 4 KiB direct mapped 16 KiB + 16 KiB 4-way set associative 1 MiB 8-way set associative (dual-core) / 2 MiB (quad-core) 2, 4 3.3 (Krait 200)
3.39 (Krait 300)
3.39 (Krait 400)
3.51 (Krait 450)
0x04D

0x06F
Swift 3 5 12 Yes VFPv4 Yes 32 × 64-bit 128-bit wide No 32 nm 32 KiB + 32 KiB 1 MiB 2 3.5 ?
Core Decode
width
Execution
ports
Pipeline
depth
Out-of-order execution FPU Pipelined
VFP
FPU
registers
NEON
(SIMD)
big.LITTLE
role
Virtualization Process
technology
L0
cache
L1
cache
L2
cache
Core
configurations
Speed
per
core
(DMIPS
/ MHz
)
ARM part number
(in the main ID register)

ARMv8-A

This is a table of 64/32-bit central processing units that implement the ARMv8-A instruction set architecture and mandatory or optional extensions of it. Most chips support the 32-bit ARMv7-A for legacy applications. All chips of this type have a floating-point unit (FPU) that is better than the one in older ARMv7-A and NEON (SIMD) chips. Some of these chips have coprocessors also include cores from the older 32-bit architecture (ARMv7). Some of the chips are SoCs and can combine both ARM Cortex-A53 and ARM Cortex-A57, such as the Samsung Exynos 7 Octa.

This list is incomplete; you can help by adding missing items. (May 2014)
Company Core Released Revision Decode Pipeline
depth
Out-of-order
execution
Branch
prediction
big.LITTLE role Exec.
ports
SIMD Fab
(in nm)
Simult. MT L0 cache L1 cache
Instr + Data
(in KiB)
L2 cache L3 cache Core
configu-
rations
Speed per core (DMIPS/
MHz
)
Clock rate ARM part number (in the main ID register)
Have it Entries
ARM Cortex-A32 (32-bit) 2017 ARMv8.0-A
(only 32-bit)
2-wide 8 No 0 ? LITTLE ? ? 28 No No 8–64 + 8–64 0–1 MiB No 1–4+ 2.3 ? 0xD01
Cortex-A34 (64-bit) 2019 ARMv8.0-A
(only 64-bit)
2-wide 8 No 0 ? LITTLE ? ? ? No No 8–64 + 8–64 0–1 MiB No 1–4+ ? ? 0xD02
Cortex-A35 2017 ARMv8.0-A 2-wide 8 No 0 Yes LITTLE ? ? 28 / 16 /
14 / 10
No No 8–64 + 8–64 0 / 128 KiB–1 MiB No 1–4+ 1.7-1.85 ? 0xD04
Cortex-A53 2014 ARMv8.0-A 2-wide 8 No 0 Conditional+
Indirect branch
prediction
big/LITTLE 2 ? 28 / 20 /
16 / 14 / 10
No No 8–64 + 8–64 128 KiB–2 MiB No 1–4+ 2.24 ? 0xD03
Cortex-A55 2017 ARMv8.2-A 2-wide 8 No 0 big/LITTLE 2 ? 28 / 20 /
16 / 14 / 12 / 10 / 5
No No 16–64 + 16–64 0–256 KiB/core 0–4 MiB 1–8+ 2.65 ? 0xD05
Cortex-A57 2013 ARMv8.0-A 3-wide 15 Yes
3-wide dispatch
? ? big 8 ? 28 / 20 /
16 / 14
No No 48 + 32 0.5–2 MiB No 1–4+ 4.1-4.8 ? 0xD07
Cortex-A65 2019 ARMv8.2-A
(only 64-bit)
2-wide 10-12 Yes
4-wide dispatch
Two-level ? 9 ? SMT2 No 32–64 + 32–64 KiB 0, 64–256 KiB 0, 0.5–4 MiB 1-8 ? ? 0xD06
Cortex-A65AE 2019 ARMv8.2-A ? ? Yes Two-level ? 2 ? SMT2 No 32–64 + 32–64 KiB 64–256 KiB 0, 0.5–4 MiB 1–8 ? ? 0xD43
Cortex-A72 2015 ARMv8.0-A 3-wide 15 Yes
5-wide dispatch
Two-level big 8 28 / 16 No No 48 + 32 0.5–4 MiB No 1–4+ 4.7-6.3 ? 0xD08
Cortex-A73 2016 ARMv8.0-A 2-wide 11–12 Yes
4-wide dispatch
Two-level big 7 28 / 16 / 10 No No 64 + 32/64 1–8 MiB No 1–4+ 4.8–8.5 ? 0xD09
Cortex-A75 2017 ARMv8.2-A 3-wide 11–13 Yes
6-wide dispatch
Two-level big 8? 2*128b 28 / 16 / 10 No No 64 + 64 256–512 KiB/core 0–4 MiB 1–8+ 6.1–9.5 ? 0xD0A
Cortex-A76 2018 ARMv8.2-A 4-wide 11–13 Yes
8-wide dispatch
128 Two-level big 8 2*128b 10 / 7 No No 64 + 64 256–512 KiB/core 1–4 MiB 1–4 6.4 ? 0xD0B
Cortex-A76AE 2018 ARMv8.2-A ? ? Yes 128 Two-level big ? ? No No ? ? ? ? ? ? 0xD0E
Cortex-A77 2019 ARMv8.2-A 4-wide 11–13 Yes
10-wide dispatch
160 Two-level big 12 2*128b 7 No 1.5K entries 64 + 64 256–512 KiB/core 1–4 MiB 1–4 7.3 ? 0xD0D
Cortex-A78 2020 ARMv8.2-A 4-wide Yes 160 Yes big 13 2*128b No 1.5K entries 32/64 + 32/64 256–512 KiB/core 1–4 MiB 1–4 7.6-8.2 ? 0xD41
Cortex-X1 2020 ARMv8.2-A 5-wide ? Yes 224 Yes big 15 4*128b No 3K entries 64 + 64 up to 1 MiB up to 8 MiB custom 10-11 ? 0xD44
Apple Cyclone 2013 ARMv8.0-A 6-wide 16 Yes 192 Yes No 9 28 No No 64 + 64 1 MiB 4 MiB 2 ? 1.3–1.4 GHz
Typhoon 2014 ARMv8.0‑A 6-wide 16 Yes Yes No 9 20 No No 64 + 64 1 MiB 4 MiB 2, 3 (A8X) ? 1.1–1.5 GHz
Twister 2015 ARMv8.0‑A 6-wide 16 Yes Yes No 9 16 / 14 No No 64 + 64 3 MiB 4 MiB
No (A9X)
2 ? 1.85–2.26 GHz
Hurricane 2016 ARMv8.0‑A 6-wide 16 Yes "big" (In A10/A10X paired with "LITTLE" Zephyr
cores)
9 3*128b 16 (A10)
10 (A10X)
No No 64 + 64 3 MiB (A10)
8 MiB (A10X)
4 MiB (A10)
No (A10X)
2x Hurricane (A10)
3x Hurricane (A10X)
? 2.34–2.36 GHz
Zephyr ARMv8.0‑A 3-wide 12 Yes LITTLE 5 16 (A10)
10 (A10X)
No No 32 + 32 1 MiB 4 MiB (A10)
No (A10X)
2x Zephyr (A10)
3x Zephyr (A10X)
? 1.09–1.3 GHz
Monsoon 2017 ARMv8.2‑A 7-wide 16 Yes "big" (In Apple A11 paired with "LITTLE" Mistral
cores)
11 3*128b 10 No No 64 + 64 8 MiB No 2x Monsoon ? 2.39 GHz
Mistral ARMv8.2‑A 3-wide 12 Yes LITTLE 5 10 No No 32 + 32 1 MiB No Mistral ? 1.19 GHz
Vortex 2018 ARMv8.3‑A 7-wide 16 Yes "big" (In Apple A12/Apple A12X/Apple A12Z paired with "LITTLE" Tempest
cores)
11 3*128b 7 No No 128 + 128 8 MiB No 2x Vortex (A12)
4x Vortex (A12X/A12Z)
? 2.49 GHz
Tempest ARMv8.3‑A 3-wide 12 Yes LITTLE 5 7 No No 32 + 32 2 MiB No 4x Tempest ? 1.59 GHz
Lightning 2019 ARMv8.4‑A 8-wide 16 Yes 560 "big" (In Apple A13 paired with "LITTLE" Thunder
cores)
11 3*128b 7 No No 128 + 128 8 MiB No 2x Lightning ? 2.65 GHz
Thunder ARMv8.4‑A 3-wide 12 Yes LITTLE 5 7 No No 96 + 48 4 MiB No 4x Thunder ? 1.8 GHz
Firestorm 2020 ARMv8.4-A 8-wide Yes 630 "big" (In Apple A14 and Apple M1/M1 Pro/M1 Max/M1 Ultra paired with "LITTLE" Icestorm
cores)
14 4*128b 5 No 192 + 128 8 MiB (A14)
12 MiB (M1)
24 MiB (M1 Pro/M1 Max)
48 MiB (M1 Ultra)
No 2x Firestorm (A14)
4x Firestorm (M1)

6x or 8x Firestorm (M1 Pro)
8x Firestorm (M1 Max)
16x Firestorm (M1 Ultra)

? 3.0–3.23 GHz
Icestorm ARMv8.4-A 4-wide Yes 110 LITTLE 7 2*128b 5 No 128 + 64 4 MiB
8 MiB (M1 Ultra)
No 4x Icestorm (A14/M1)
2x Icestorm (M1 Pro/Max)
4x Icestorm (M1 Ultra)
? 1.82–2.06 GHz
Avalanche 2021 ARMv8.6‑A 8-wide Yes "big" (In Apple A15 and Apple M2/M2 Pro/M2 Max/M2 Ultra paired with "LITTLE" Blizzard
cores)
14 4*128b 5 No 192 + 128 12 MiB (A15)
16 MiB (M2)
32 MiB (M2 Pro/M2 Max)
64 MiB (M2 Ultra)
No 2x Avalanche (A15)
4x Avalanche (M2)
6x or 8x Avalanche (M2 Pro)

8x Avalanche (M2 Max)
16x Avalanche (M2 Ultra)

? 2.93–3.49 GHz
Blizzard ARMv8.6‑A 4-wide Yes LITTLE 8 2*128b 5 No 128 + 64 4 MiB
8 MiB (M2 Ultra)
No 4x Blizzard ? 2.02–2.42 GHz
Everest 2022 ARMv8.6‑A 8-wide Yes "big" (In Apple A16 paired with "LITTLE" Sawtooth
cores)
14 4*128b 5 No 192 + 128 16 MiB No 2x Everest ? 3.46 GHz
Sawtooth ARMv8.6‑A 4-wide Yes LITTLE 8 2*128b 5 No 128 + 64 4 MiB No 4x Sawtooth ? 2.02 GHz
Nvidia Denver 2014 ARMv8‑A 2-wide hardware
decoder, up to
7-wide variable-
length VLIW
micro-ops
13 Not if the hardware
decoder is in use.
Can be provided
by dynamic software
translation into VLIW.
Direct+
Indirect branch
prediction
No 7 28 No No 128 + 64 2 MiB No 2 ? ?
Denver 2 2016 ARMv8‑A ? 13 Not if the hardware
decoder is in use.
Can be provided
by dynamic software
translation into VLIW.
Direct+
Indirect branch
prediction
"Super" Nvidia's own implementation ? 16 No No 128 + 64 2 MiB No 2 ? ?
Carmel 2018 ARMv8.2‑A ? Direct+
Indirect branch
prediction
? 12 No No 128 + 64 2 MiB (4 MiB @ 8 cores) 2 (+ 8) 6.5-7.4 ?
Cavium ThunderX 2014 ARMv8-A 2-wide 9 Yes Two-level ? 28 No No 78 + 32 16 MiB No 8–16, 24–48 ? ?
ThunderX2
(ex. Broadcom Vulcan)
2018 ARMv8.1-A
4-wide
"4 μops"
? Yes Multi-level ? ? 16 SMT4 No 32 + 32
(data 8-way)
256 KiB
per core
1 MiB
per core
16–32 ? ?
Marvell ThunderX3 2020 ARMv8.3+ 8-wide ? Yes
4-wide dispatch
Multi-level ? 7 7 SMT4 ? 64 + 32 512 KiB
per core
90 MiB 60 ? ?
Applied

Micro

Helix 2014 ? ? ? ? ? ? ? 40 / 28 No No 32 + 32 (per core;
write-through
w/parity)
256 KiB shared
per core pair (with ECC)
1 MiB/core 2, 4, 8 ? ?
X-Gene 2013 ? 4-wide 15 Yes ? ? ? 40 No No 8 MiB 8 4.2 ?
X-Gene 2 2015 ? 4-wide 15 Yes ? ? ? 28 No No 8 MiB 8 4.2 ?
X-Gene 3 2017 ? ? ? ? ? ? ? 16 No No ? ? 32 MiB 32 ? ?
Qualcomm Kryo 2015 ARMv8-A ? ? Yes Two-level? "big" or "LITTLE"
Qualcomm's own similar implementation
? 14 No No 32+24 0.5–1 MiB 2+2 6.3 ?
Kryo 200 2016 ARMv8-A 2-wide 11–12 Yes
7-wide dispatch
Two-level big 7 14 / 11 / 10 / 6 No No 64 + 32/64? 512 KiB/Gold Core No 4 ? 1.8–2.45 GHz
2-wide 8 No 0 Conditional+
Indirect branch
prediction
LITTLE 2 8–64? + 8–64? 256 KiB/Silver Core 4 ? 1.8–1.9 GHz
Kryo 300 2017 ARMv8.2-A 3-wide 11–13 Yes
8-wide dispatch
Two-level big 8 10 No No 64+64 256 KiB/Gold Core 2 MiB 2, 4 ? 2.0–2.95 GHz
2-wide 8 No 0 Conditional+
Indirect branch
prediction
LITTLE 28 16–64? + 16–64? 128 KiB/Silver 4, 6 ? 1.7–1.8 GHz
Kryo 400 2018 ARMv8.2-A 4-wide 11–13 Yes
8-wide dispatch
Yes big 8 11 / 8 / 7 No No 64 + 64 512 KiB/Gold Prime

256 KiB/Gold

2 MiB 2, 1+1, 4, 1+3 ? 2.0–2.96 GHz
2-wide 8 No 0 Conditional+
Indirect branch
prediction
LITTLE 2 16–64? + 16–64? 128 KiB/Silver 4, 6 ? 1.7–1.8 GHz
Kryo 500 2019 ARMv8.2-A 4-wide 11–13 Yes
8-wide dispatch
Yes big 8 / 7 No ? 512 KiB/Gold Prime

256 KiB/Gold

3 MiB 2, 1+3 ? 2.0–3.2 GHz
2-wide 8 No 0 Conditional+
Indirect branch
prediction
LITTLE 2 ? 128 KiB/Silver 4, 6 ? 1.7–1.8 GHz
Kryo 600 2020 ARMv8.4-A 4-wide 11–13 Yes
8-wide dispatch
Yes big 6 / 5 No ? 64 + 64 1024 KiB/Gold Prime

512 KiB/Gold

4 MiB 2, 1+3 ? 2.2–3.0 GHz
2-wide 8 No 0 Conditional+
Indirect branch
prediction
LITTLE 2 ? 128 KiB/Silver 4, 6 ? 1.7–1.8 GHz
Falkor 2017 "ARMv8.1-A features"; AArch64 only (not 32-bit) 4-wide 10–15 Yes
8-wide dispatch
Yes ? 8 10 No 24 KiB 88 + 32 500KiB 1.25MiB 40–48 ? ?
Samsung M1 2016 ARMv8-A 4-wide 13 Yes
9-wide dispatch
96 big 8 14 No No 64 + 32 2 MiB No 4 ? 2.6 GHz
M2 2017 ARMv8-A 4-wide 100 Two-level big 10 No No 64 + 64 2 MiB No 4 ? 2.3 GHz
M3 2018 ARMv8.2-A 6-wide 15 Yes
12-wide dispatch
228 Two-level big 12 10 No No 64 + 64 512 KiB per core 4096KB 4 ? 2.7 GHz
M4 2019 ARMv8.2-A 6-wide 15 Yes
12-wide dispatch
228 Two-level big 12 8 / 7 No No 64 + 64 512 KiB per core 3072KB 2 ? 2.73 GHz
M5 2020 ARMv8.2-A 6-wide Yes
12-wide dispatch
228 Two-level big 7 No No 64 + 64 512 KiB per core 3072KB 2 ? 2.73 GHz
Fujitsu A64FX 2019 ARMv8.2-A 4/2-wide 7+ Yes
5-way?
Yes n/a 8+ 2*512b 7 No No 64 + 64 8MiB per 12+1 cores No 48+4 ? 1.9 GHz+
HiSilicon TaiShan V110 2019 ARMv8.2-A 4-wide ? Yes n/a 8 7 No No 64 + 64 512 KiB per core 1 MiB per core ? ? ?
Company Core Released Revision Decode Pipeline
depth
Out-of-order
execution
Branch
prediction
big.LITTLE role Exec. ports SIMD Fab
(in nm)
Simult. MT L0 cache L1 cache
Instr + Data
(in KiB)
L2 cache L3 cache Core
configu-
rations
Speed per core (DMIPS/
MHz
)
Clock rate ARM part number (in the main ID register)

ARMv9-A

Company Core Released Revision Decode Pipeline depth Out-of-order execution Branch
prediction
big.LITTLE role Exec. ports SIMD Fab
(in nm)
Simult. MT L0 cache L1 cache
Instr + Data
(in KiB)
L2 cache L3 cache Core
configu-
rations
Speed per core (DMIPS/
MHz
)
Clock rate ARM part number (in the main ID register)
Have it Entries
Arm Holdings ? October 2024 ARMv9.6-A ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?

ARMv9-M

Company Core Released Revision Decode Pipeline depth Out-of-order execution Branch
prediction
big.LITTLE role Exec. ports SIMD Fab
(in nm)
Simult. MT L0 cache L1 cache
Instr + Data
(in KiB)
L2 cache L3 cache Core
configu-
rations
Speed per core (DMIPS/
MHz
)
Clock rate ARM part number (in the main ID register)
Have it Entries

ARMv9-R

Company Core Released Revision Decode Pipeline depth Out-of-order execution Branch
prediction
big.LITTLE role Exec. ports SIMD Fab
(in nm)
Simult. MT L0 cache L1 cache
Instr + Data
(in KiB)
L2 cache L3 cache Core
configu-
rations
Speed per core (DMIPS/
MHz
)
Clock rate ARM part number (in the main ID register)
Have it Entries

See also

Notes

  1. ^ As Dhrystone (implied in "DMIPS") is a synthetic benchmark developed in 1980s, it is no longer representative of prevailing workloads – use with caution.

References

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ARM-based chips
Application ARM-based chips
Application
processors
(32-bit)
ARMv7-A
Cortex-A5
Cortex-A7
Cortex-A8
Cortex-A9
Cortex-A15
Cortex-A17
Others
ARMv7-A
compatible
ARMv8-A
Others
Application
processors
(64-bit)
ARMv8-A
Cortex-A35
Cortex-A53
Cortex-A57
Cortex-A72
Cortex-A73
Others
ARMv8-A
compatible
ARMv8.1-A
ARMv8.1-A
compatible
ARMv8.2-A
Cortex-A55
Cortex-A75
Cortex-A76
Cortex-A77
Cortex-A78
Cortex-X1
Neoverse N1
Others
  • Cortex-A65, Cortex-A65AE, Cortex-A76AE, Cortex-A78C, Cortex-X1C, Neoverse E1
ARMv8.2-A
compatible
ARMv8.3-A
ARMv8.3-A
compatible
ARMv8.4-A
Neoverse V1
ARMv8.4-A
compatible
ARMv8.5-A
ARMv8.5-A
compatible
ARMv8.6-A
ARMv8.6-A
compatible
ARMv8.7-A
ARMv8.7-A
compatible
ARMv9.0-A
Cortex-A510
Cortex-A710
Cortex-A715
Cortex-X2
Cortex-X3
Neoverse N2
Neoverse V2
ARMv9.2-A
Cortex-A520
Cortex-A720
Cortex-X4
Cortex-X925
Neoverse N3-
Neoverse V3-
ARMv9.2-A
compatible
Embedded ARM-based chips
Embedded
microcontrollers
Cortex-M0
  • Cypress PSoC 4000, 4100, 4100M, 4200, 4200DS, 4200L, 4200M
  • Infineon XMC1000
  • Nordic nRF51
  • NXP LPC1100, LPC1200
  • nuvoTon NuMicro
  • Sonix SN32F700
  • STMicroelectronics STM32 F0
  • Toshiba TX00
  • Vorago VA108x0
Cortex-M0+
  • Cypress PSoC 4000S, 4100S, 4100S+, 4100PS, 4700S, FM0+
  • Holtek HT32F52000
  • Microchip (Atmel) SAM C2, D0, D1, D2, DA, L2, R2, R3
  • NXP LPC800, LPC11E60, LPC11U60
  • NXP (Freescale) Kinetis E, EA, L, M, V1, W0
  • Raspberry Pi RP2040
  • Renesas Synergy S1
  • Silicon Labs (Energy Micro) EFM32 Zero, Happy
  • STMicroelectronics STM32 L0
Cortex-M1
  • Altera FPGAs Cyclone-II, Cyclone-III, Stratix-II, Stratix-III
  • Microsemi (Actel) FPGAs Fusion, IGLOO/e, ProASIC3L, ProASIC3/E
  • Xilinx FPGAs Spartan-3, Virtex-2-3-4
Cortex-M3
Cortex-M4
  • Microchip (Atmel) SAM 4L, 4N, 4S
  • NXP (Freescale) Kinetis K, W2
  • Renesas RA4W1, RA6M1, RA6M2, RA6M3, RA6T1
Cortex-M4F
  • Cypress 6200, FM4
  • Infineon XMC4000
  • Microchip (Atmel) SAM 4C, 4E, D5, E5, G5
  • Microchip CEC1302
  • Nordic nRF52
  • NXP LPC4000, LPC4300
  • NXP (Freescale) Kinetis K, V3, V4
  • Renesas Synergy S3, S5, S7
  • Silicon Labs (Energy Micro) EFM32 Wonder
  • STMicroelectronics STM32 F3, F4, L4, L4+, WB
  • Texas Instruments LM4F/TM4C, MSP432
  • Toshiba TX04
Cortex-M7F
  • Microchip (Atmel) SAM E7, S7, V7
  • NXP (Freescale) Kinetis KV5x, i.MX RT 10xx, i.MX RT 11xx, S32K3xx
  • STMicroelectronics STM32 F7, H7
Cortex-M23
  • GigaDevice CD32E2xx
  • Microchip (Atmel) SAM L10, L11, and PIC 32CM-LE 32CM-LS
  • Nuvoton M23xx family, M2xx family, NUC1262, M2L31
  • Renesas S1JA, RA2A1, RA2L1, RA2E1, RA2E2
Cortex-M33F
  • Analog Devices ADUCM4
  • Dialog DA1469x
  • GigaDevice GD32E5, GD32W5
  • Nordic nRF91, nRF5340, nRF54
  • NXP LPC5500, i.MX RT600
  • ON RSL15
  • Renesas RA4, RA6
  • ST STM32 H5, L5, U5, WBA
  • Silicon Labs Wireless Gecko Series 2
Cortex-M35P
  • STMicroelectronics ST33K
Cortex-M55F
Cortex-M85F
  • Renesas RA8
Real-time
microprocessors
Cortex-R4F
  • Texas Instruments RM4, TMS570
  • Renesas RZ/T1
Cortex-R5F
Cortex-R7F
  • Renesas RZ/G2E, RZ/G2H, RZ/G2M, RZ/G2N
Cortex-R52F
  • NXP S32Z, S32E
  • Renesas RZ/N2L, RZ/T2L, RZ/T2M
Cortex-R52+F
  • STMicroelectronics Stellar G, Stellar P
Classic ARM-based chips
Classic
processors
ARM7
ARM9
ARM11
ARMv2a
compatible
ARMv4
compatible
ARMv5TE
compatible
  • Intel/Marvell XScale
  • Marvell Sheeva, Feroceon, Jolteon, Mohawk
  • Faraday FA606TE, FA616TE, FA626TE, FA726TE
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