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AMD Excavator Family 15h is a microarchitecture developed by AMD to succeed Steamroller Family 15h for use in AMD APU processors and normal CPUs. On October 12, 2011, AMD revealed Excavator to be the code name for the fourth-generation Bulldozer-derived core.

The Excavator-based APU for mainstream applications is called Carrizo and was released in 2015. The Carrizo APU is designed to be HSA 1.0 compliant. An Excavator-based APU and CPU variant named Toronto for server and enterprise markets was also produced.

Excavator was the final revision of the "Bulldozer" family, with two new microarchitectures replacing Excavator a year later. Excavator was succeeded by the x86-64 Zen architecture in early 2017.

Architecture

Excavator added hardware support for new instructions such as AVX2, BMI2 and RDRAND. Excavator is designed using High Density (aka "Thin") Libraries normally used for GPUs to reduce electric energy consumption and die size, delivering a 30 percent increase in efficient energy use. Excavator can process up to 15% more instructions per clock compared to AMD's previous core Steamroller.

AMD's Fusion Controller Hub has been discontinued since the release of the Carrizo series of CPUs as it has been integrated into the same die as the rest of the CPU.

Features and ASICs

The following table shows features of AMD's processors with 3D graphics, including APUs (see also: List of AMD processors with 3D graphics).

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Platform			High, standard and low power														Low and ultra-low power
Codename	Server	Basic						Toronto
		Micro																Kyoto
	Desktop	Performance													Raphael	Phoenix
		Mainstream	Llano	Trinity	Richland	Kaveri	Kaveri Refresh (Godavari)	Carrizo	Bristol Ridge	Raven Ridge	Picasso	Renoir	Cezanne
		Entry
		Basic																Kabini				Dalí
	Mobile	Performance										Renoir	Cezanne	Rembrandt	Dragon Range
		Mainstream	Llano	Trinity	Richland	Kaveri		Carrizo	Bristol Ridge	Raven Ridge	Picasso	Renoir Lucienne	Cezanne Barceló			Phoenix
		Entry																				Dalí			Mendocino
		Basic															Desna, Ontario, Zacate	Kabini, Temash	Beema, Mullins	Carrizo-L	Stoney Ridge		Pollock
	Embedded			Trinity		Bald Eagle		Merlin Falcon, Brown Falcon		Great Horned Owl		Grey Hawk					Ontario, Zacate	Kabini	Steppe Eagle, Crowned Eagle, LX-Family		Prairie Falcon	Banded Kestrel		River Hawk
Released			Aug 2011	Oct 2012	Jun 2013	Jan 2014	2015	Jun 2015	Jun 2016	Oct 2017	Jan 2019	Mar 2020	Jan 2021	Jan 2022	Sep 2022	Jan 2023	Jan 2011	May 2013	Apr 2014	May 2015	Feb 2016	Apr 2019	Jul 2020	Jun 2022	Nov 2022
CPU microarchitecture			K10	Piledriver		Steamroller		Excavator	"Excavator+"	Zen	Zen+	Zen 2	Zen 3	Zen 3+	Zen 4		Bobcat	Jaguar	Puma	Puma+	"Excavator+"	Zen		Zen+	"Zen 2+"
ISA			x86-64 v1	x86-64 v2				x86-64 v3							x86-64 v4		x86-64 v1	x86-64 v2			x86-64 v3
Socket	Desktop	Performance	—												AM5	—	—
		Mainstream	—					AM4						—		—
		Entry	FM1	FM2		FM2+		FM2+, AM4	AM4					—
		Basic	—														—	AM1	—			FP5	—
	Other		FS1	FS1+, FP2		FP3		FP4		FP5		FP6		FP7	FL1	FP7 FP7r2 FP8	?	FT1	FT3	FT3b		FP4	FP5	FT5	FP5	FT6
PCI Express version			2.0			3.0								4.0	5.0	4.0	2.0				3.0
CXL			—														—
Fab. (nm)			GF 32SHP (HKMG SOI)			GF 28SHP (HKMG bulk)				GF 14LPP (FinFET bulk)	GF 12LP (FinFET bulk)	TSMC N7 (FinFET bulk)		TSMC N6 (FinFET bulk)	CCD: TSMC N5 (FinFET bulk) cIOD: TSMC N6 (FinFET bulk)	TSMC 4nm (FinFET bulk)	TSMC N40 (bulk)	TSMC N28 (HKMG bulk)	GF 28SHP (HKMG bulk)			GF 14LPP (FinFET bulk)		GF 12LP (FinFET bulk)	TSMC N6 (FinFET bulk)
Die area (mm)			228	246		245		245	250	210		156	180	210	CCD: (2x) 70 cIOD: 122	178	75 (+ 28 FCH)	107		?	125	149			~100
Min TDP (W)			35	17				12				10		15	65	35	4.5	4	3.95	10	6			12	8
Max APU TDP (W)			100			95		65						45	170	54	18	25					6	54	15
Max stock APU base clock (GHz)			3	3.8	4.1	4.1		3.7	3.8	3.6	3.7	3.8	4.0	3.3	4.7	4.3	1.75	2.2	2	2.2	3.2	2.6	1.2	3.35	2.8
Max APUs per node			1														1
Max core dies per CPU			1												2	1	1
Max CCX per core die			1									2	1				1
Max cores per CCX			4										8				2	4			2			4
Max CPU cores per APU			4									8			16	8	2	4			2			4
Max threads per CPU core			1							2							1					2
Integer pipeline structure			3+3	2+2						4+2		4+2+1	1+3+3+1+2				1+1+1+1				2+2	4+2			4+2+1
i386, i486, i586, CMOV, NOPL, i686, PAE, NX bit, CMPXCHG16B, AMD-V, RVI, ABM, and 64-bit LAHF/SAHF
IOMMU			—	v2													v1		v2
BMI1, AES-NI, CLMUL, and F16C																	—
MOVBE			—
AVIC, BMI2, RDRAND, and MWAITX/MONITORX																	—
SME, TSME, ADX, SHA, RDSEED, SMAP, SMEP, XSAVEC, XSAVES, XRSTORS, CLFLUSHOPT, CLZERO, and PTE Coalescing			—														—
GMET, WBNOINVD, CLWB, QOS, PQE-BW, RDPID, RDPRU, and MCOMMIT			—														—
MPK, VAES			—														—
SGX			—														—
FPUs per core			1	0.5						1							1				0.5	1
Pipes per FPU			2														2
FPU pipe width			128-bit									256-bit					80-bit	128-bit							256-bit
CPU instruction set SIMD level			SSE4a	AVX				AVX2							AVX-512		SSSE3	AVX			AVX2
3DNow!			3DNow!+	—													—
PREFETCH/PREFETCHW
GFNI			—														—
AMX			—
FMA4, LWP, TBM, and XOP			—							—							—					—
FMA3
AMD XDNA			—														—
L1 data cache per core (KiB)			64	16				32									32
L1 data cache associativity (ways)			2	4				8									8
L1 instruction caches per core			1	0.5						1							1				0.5	1
Max APU total L1 instruction cache (KiB)			256	128		192				256					512	256	64		128		96	128
L1 instruction cache associativity (ways)			2			3				4		8					2				3	4			8
L2 caches per core			1	0.5						1							1				0.5	1
Max APU total L2 cache (MiB)			4					2				4			16		1	2			1			2
L2 cache associativity (ways)			16							8							16					8
Max on--die L3 cache per CCX (MiB)			—							4			16		32		—						4
Max 3D V-Cache per CCD (MiB)										—					64	—							—
Max total in-CCD L3 cache per APU (MiB)										4		8	16		64								4
Max. total 3D V-Cache per APU (MiB)										—					64	—							—
Max. board L3 cache per APU (MiB)										—													—
Max total L3 cache per APU (MiB)										4		8	16		128								4
APU L3 cache associativity (ways)										16													16
L3 cache scheme										Victim													Victim
Max. L4 cache			—														—
Max stock DRAM support			DDR3-1866		DDR3-2133			DDR3-2133, DDR4-2400	DDR4-2400	DDR4-2933		DDR4-3200, LPDDR4-4266		DDR5-4800, LPDDR5-6400	DDR5-5200	DDR5-5600, LPDDR5x-7500	DDR3L-1333	DDR3L-1600	DDR3L-1866		DDR3-1866, DDR4-2400	DDR4-2400	DDR4-1600	DDR4-3200	LPDDR5-5500
Max DRAM channels per APU			2														1					2	1	2
Max stock DRAM bandwidth (GB/s) per APU			29.866		34.132			38.400		46.932		68.256		102.400	83.200	120.000	10.666	12.800	14.933		19.200	38.400	12.800	51.200	88.000
GPU microarchitecture			TeraScale 2 (VLIW5)	TeraScale 3 (VLIW4)		GCN 2nd gen		GCN 3rd gen		GCN 5th gen				RDNA 2		RDNA 3	TeraScale 2 (VLIW5)	GCN 2nd gen			GCN 3rd gen	GCN 5th gen			RDNA 2
GPU instruction set			TeraScale instruction set			GCN instruction set								RDNA instruction set			TeraScale instruction set	GCN instruction set							RDNA instruction set
Max stock GPU base clock (MHz)			600	800	844	866		1108		1250	1400	2100		2400	400		538	600	?	847	900	1200	600	1300	1900
Max stock GPU base GFLOPS			480	614.4	648.1	886.7		1134.5		1760	1971.2	2150.4		3686.4	102.4		86	?	?	?	345.6	460.8	230.4	1331.2	486.4
3D engine			Up to 400:20:8	Up to 384:24:6		Up to 512:32:8				Up to 704:44:16		Up to 512:32:8		768:48:8	128:8:4		80:8:4	128:8:4			Up to 192:12:8	Up to 192:12:4	192:12:4	Up to 512:?:?	128:?:?
			IOMMUv1			IOMMUv2											IOMMUv1		?		IOMMUv2
Video decoder			UVD 3.0			UVD 4.2		UVD 6.0		VCN 1.0		VCN 2.1	VCN 2.2	VCN 3.1		?	UVD 3.0	UVD 4.0	UVD 4.2		UVD 6.2	VCN 1.0			VCN 3.1
Video encoder			—	VCE 1.0		VCE 2.0		VCE 3.1									—	VCE 2.0			VCE 3.4
AMD Fluid Motion
GPU power saving			PowerPlay	PowerTune													PowerPlay	PowerTune
TrueAudio			—										?				—
FreeSync						1 2												1 2
HDCP			?			1.4				2.2				2.3			?	1.4				2.2			2.3
PlayReady			—							3.0 not yet							—					3.0 not yet
Supported displays			2–3	2–4				3		3 (desktop) 4 (mobile, embedded)		4					2				3	4		4
/drm/radeon									—												—
/drm/amdgpu			—														—

1. For FM2+ Excavator models: A8-7680, A6-7480 & Athlon X4 845.
2. A PC would be one node.
3. An APU combines a CPU and a GPU. Both have cores.
4. Requires firmware support.
5. ^ Requires firmware support.
6. No SSE4. No SSSE3.
7. Single-precision performance is calculated from the base (or boost) core clock speed based on a FMA operation.
8. Unified shaders : texture mapping units : render output units
9. ^ To play protected video content, it also requires card, operating system, driver, and application support. A compatible HDCP display is also needed for this. HDCP is mandatory for the output of certain audio formats, placing additional constraints on the multimedia setup.
10. To feed more than two displays, the additional panels must have native DisplayPort support. Alternatively active DisplayPort-to-DVI/HDMI/VGA adapters can be employed.
11. ^ DRM (Direct Rendering Manager) is a component of the Linux kernel. Support in this table refers to the most current version.

Processors

APU lines

There are three APU lines announced or released:

1. Budget and mainstream markets (desktop and mobile): Carrizo APU
   • The Carrizo mobile APUs were launched in 2015 based on Excavator x86 cores and featuring Heterogeneous System Architecture for integrated task sharing between CPUs and GPUs, which allows a GPU to perform compute functions, which is claimed provide greater performance increases than shrinking the feature size alone.
   • Carrizo desktop APUs were launched in 2018. The mainstream product (A8-7680) has 4 Excavator cores and a GPU based on GCN1.2 architecture. Also, an entry-level APU (A6-7480) with 2 Excavator cores is also launched.
2. Budget and mainstream markets (desktop and mobile): Bristol Ridge, and Stoney Ridge (for entry level notebooks), APUs
   • Bristol Ridge APUs utilize socket AM4 and DDR4 RAM
   • Bristol Ridge APUs have up to 4 Excavator CPU cores and up to 8 3rd generation GCN GPU cores
   • Up to a 20% CPU performance increase over Carrizo
   • TDP of 15W to 65W, 15–35W for mobile
3. Enterprise and server markets: Toronto APU
   • The Toronto APU for server and enterprise markets featured four x86 Excavator CPU core modules and Volcanic Islands integrated GPU core.
   • The Excavator cores has a greater advantage with IPC than Steamroller. The improvement is 4–15%.
   • Support for HSA/hUMA, DDR3/DDR4, PCIe 3.0, GCN 1.2
   • The Toronto APU was available in BGA and SoC variants. The SoC variant had the southbridge on the same die as the APU to save space and power and to optimize workloads.
   • A complete system with a Toronto APU would have a maximum power usage of 70 W.

CPU Desktop lines

There are no CPUs built on Steamroller (3rd gen Bulldozer) or Excavator (4th gen Bulldozer) architectures on high-end desktop platforms.

Excavator CPU for Desktop announced on 2nd Feb 2016, named Athlon X4 845. In 2017, three more desktop CPUs (Athlon X4 9x0) were launched. They come in Socket AM4, with a TDP of 65W. In fact, they are APUs with their graphics cores disabled.

Server lines

The AMD Opteron roadmaps for 2015 show the Excavator-based Toronto APU and Toronto CPU intended for 1 Processor (1P) cluster applications:

• For 1P Web and Enterprise Services Clusters:
  • Toronto CPU – quad-core x86 Excavator architecture
  • plans for Cambridge CPU – 64-bit AArch64 core
• For 1P Compute and Media Clusters:
  • Toronto APU – quad-core x86 Excavator architecture
• For 2P/4P Servers:
  • Warsaw CPU – 12/16 core x86 Piledriver (2nd gen Bulldozer) (Opteron 6338P and 6370P)
  • no plans for Steamroller (3rd gen Bulldozer) or Excavator (4th gen Bulldozer) architectures on high-end multi-processor platforms

References

1. "Computex 2015: AMD launches Carrizo A-Series processors". ZDNet.
2. "AMD leak confirms that Excavator APU will be 28nm, and that some production is moving back to GlobalFoundries - ExtremeTech". www.extremetech.com.
3. Reynolds, Sam (October 31, 2013). "New confirmed details on AMD's 2014 APU lineup, Kaveri delayed". Vr-zone.com. Archived from the original on January 25, 2014. Retrieved November 24, 2013.
4. "AMD updates product roadmap for 2014 and 2015". Digitimes.com. August 26, 2013. Retrieved November 24, 2013.
5. ^ Hachman, Mark (November 21, 2014). "AMD reveals high-end 'Carrizo' APU, the first chip to fully embrace audacious HSA tech". PCWorld. Retrieved January 15, 2015.
6. ^ Mujtaba, Hassan (December 26, 2013). "AMD Opteron Roadmap Reveals Next Generation Toronto and Carrizo APU Details". WCCF Tech. Retrieved January 15, 2015.
7. "AMD hints at high-performance Zen x86 architecture | bit-tech.net". bit-tech.net.
8. "AMD to Introduce New High-Performance Micro-Architecture in 2015 – Report - X-bit labs". Archived from the original on 2014-05-13. Retrieved 2014-05-22.
9. Moammer, Khalid (September 9, 2014). "AMD's Next Gen x86 High Performance Core is Zen". WCCF Tech. Retrieved January 15, 2015.
10. ^ Mujtaba, Hassan (May 5, 2014). "AMD Announces 2014-2016 Roadmap – 20nm Project SkyBridge and K12 64-bit ARM Cores For 2016". WCCF Tech. Retrieved January 15, 2015.
11. "AMDs Carrizo architecture detailed and explored". Extremetech.com. June 2, 2015. Retrieved March 3, 2019.
12. Crowthers, Doug (August 28, 2012). "AMD Explains Advantages of High Density (Thin) Libraries". Tom's Hardware.
13. Mujtaba, Hassan (August 26, 2015). "AMD Details Carrizo APUs Energy Efficient Design at Hot Chips 2015 - 28nm Bulk High Density Design With 3.1 Billion Transistors, 250mm2 Die".
14. "AMD at ISSCC 2015: Carrizo and Excavator Details".
15. "AMD Announces the 7th Generation APU: Excavator mk2 in Bristol Ridge and Stoney Ridge for Notebooks". 31 May 2016. Retrieved 3 January 2020.
16. "AMD Mobile "Carrizo" Family of APUs Designed to Deliver Significant Leap in Performance, Energy Efficiency in 2015" (Press release). 20 November 2014. Retrieved 16 February 2015.
17. "The Mobile CPU Comparison Guide Rev. 13.0 Page 5 : AMD Mobile CPU Full List". TechARP.com. Retrieved 13 December 2017.
18. ^ "AMD VEGA10 and VEGA11 GPUs spotted in OpenCL driver". VideoCardz.com. Retrieved 6 June 2017.
19. Cutress, Ian (1 February 2018). "Zen Cores and Vega: Ryzen APUs for AM4 – AMD Tech Day at CES: 2018 Roadmap Revealed, with Ryzen APUs, Zen+ on 12nm, Vega on 7nm". Anandtech. Retrieved 7 February 2018.
20. Larabel, Michael (17 November 2017). "Radeon VCN Encode Support Lands in Mesa 17.4 Git". Phoronix. Retrieved 20 November 2017.
21. ^ "AMD Ryzen 5000G 'Cezanne' APU Gets First High-Res Die Shots, 10.7 Billion Transistors In A 180mm2 Package". wccftech. Aug 12, 2021. Retrieved August 25, 2021.
22. Tony Chen; Jason Greaves, "AMD's Graphics Core Next (GCN) Architecture" (PDF), AMD, retrieved 13 August 2016
23. "A technical look at AMD's Kaveri architecture". Semi Accurate. Retrieved 6 July 2014.
24. "How do I connect three or More Monitors to an AMD Radeon™ HD 5000, HD 6000, and HD 7000 Series Graphics Card?". AMD. Retrieved 8 December 2014.
25. Airlie, David (26 November 2009). "DisplayPort supported by KMS driver mainlined into Linux kernel 2.6.33". Retrieved 16 January 2016.
26. "Radeon feature matrix". freedesktop.org. Retrieved 10 January 2016.
27. Deucher, Alexander (16 September 2015). "XDC2015: AMDGPU" (PDF). Retrieved 16 January 2016.
28. ^ Michel Dänzer (17 November 2016). "[ANNOUNCE] xf86-video-amdgpu 1.2.0". lists.x.org.
29. Cutress, Ian (1 June 2016). "AMD Announces 7th Generation APU". Anandtech.com. Retrieved 1 June 2016.
30. Jeff Kampman (2 February 2016). "AMD puts Excavator on the desktop with the Athlon X4 845".

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