Misplaced Pages

Inter-processor interrupt

Article snapshot taken from Wikipedia with creative commons attribution-sharealike license. Give it a read and then ask your questions in the chat. We can research this topic together.
Type of interrupt signal sent between computer processors
This article needs additional citations for verification. Please help improve this article by adding citations to reliable sources. Unsourced material may be challenged and removed.
Find sources: "Inter-processor interrupt" – news · newspapers · books · scholar · JSTOR (December 2014) (Learn how and when to remove this message)

In computing, an inter-processor interrupt (IPI), also known as a shoulder tap, is a special type of interrupt by which one processor may interrupt another processor in a multiprocessor system if the interrupting processor requires action from the other processor. Actions that might be requested include:

  • flushes of memory management unit caches, such as translation lookaside buffers, on other processors when memory mappings are changed by one processor;
  • stopping when the system is being shut down by one processor.
  • Notify a processor that higher priority work is available.
  • Notify a processor of work that cannot be done on all processors due to, e.g.,
    • asymmetric access to I/O channels
    • special features on some processors

Mechanism

The M65MP option of OS/360 used the Direct Control feature of the S/360 to generate an interrupt on another processor; on S/370 and its successors, including z/Architecture, the SIGNAL PROCESSOR instruction provides a more formalized interface. The documentation for some IBM operating systems refers to this as a shoulder tap.

On IBM PC compatible computers that use the Advanced Programmable Interrupt Controller (APIC), IPI signaling is often performed using the APIC. When a CPU wishes to send an interrupt to another CPU, it stores the interrupt vector and the identifier of the target's local APIC in the Interrupt Command Register (ICR) of its own local APIC. A message is then sent via the APIC bus to the target's local APIC, which then issues a corresponding interrupt to its own CPU.

Examples

In a multiprocessor system running Microsoft Windows, a processor may interrupt another processor for the following reasons, in addition to the ones listed above:

  1. queue a DISPATCH_LEVEL interrupt to schedule a particular thread for execution;
  2. kernel debugger breakpoint.

IPIs are given an IRQL of 29.

See also

References

  1. "Appendix F: Multiprocessing Extensions" (PDF). OS I/O Supervisor Logic - Release 21 - Program Number 360S-CI-505 (PDF). Program Logic. IBM. p. 271. GY28-6616-9. Retrieved August 28, 2022.
  2. "AMD Technical Information Portal". docs.amd.com. Retrieved 2024-07-18.
  3. "Inter Processor Interrupt usage". Stack Overflow. Retrieved 2024-07-18.
  4. Matt (2002-04-28). "Understanding IRQL". Archived from the original on 2019-10-14. Retrieved 2014-12-06.

External links


Stub icon

This computer hardware article is a stub. You can help Misplaced Pages by expanding it.

Categories: