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The KOMDIV-32 (Russian: КОМДИВ-32) is a family of 32-bit microprocessors developed and manufactured by the Scientific Research Institute of System Development (NIISI) of the Russian Academy of Sciences. The manufacturing plant of NIISI is located in Dubna on the grounds of the Kurchatov Institute. The KOMDIV-32 processors are intended primarily for spacecraft applications and many of them are radiation hardened (rad-hard).

These microprocessors are compatible with MIPS R3000 and have an integrated MIPS R3010 compatible floating-point unit.

Overview

Details

1V812

• 0.5 μm CMOS process, 3-layer metal
• 108-pin ceramic Quad Flat Package (QFP)
• 1.5 million transistors, 8KB L1 instruction cache, 8KB L1 data cache, compatible with IDT 79R3081E

1890VM1T

• 0.5 μm CMOS process

1890VM2T

• 0.35 μm CMOS process

1990VM2T

• 0.35 μm silicon on insulator (SOI) CMOS process
• 108-pin ceramic Quad Flat Package (QFP)
• working temperature from -60 to 125 °C

5890VM1Т

• 0.5 μm silicon on insulator (SOI) CMOS process
• 108-pin ceramic Quad Flat Package (QFP)
• cache (8KB each for data and instructions)
• working temperature from -60 to 125 °C

5890VE1Т

• 0.5 μm SOI CMOS process
• 240-pin ceramic QFP
• radiation tolerance to not less than 200 kRad, working temperature from -60 to 125 °C
• System-on-a-chip (SoC) including PCI master / slave, 16 GPIO, 3 UART, 3 32-bit timers
• cache (8KB each for data and instructions)
• second-sourced by MVC Nizhny Novgorod under the name 1904VE1T (Russian: 1904ВЕ1Т) with a clock rate of 40 MHz

1900VM2T

• development name Rezerv-32
• 0.35 μm SOI CMOS process
• 108-pin ceramic QFP
• radiation tolerance to not less than 200 kRad, working temperature from -60 to 125 °C
• triple modular redundancy on block level with self-healing
• both registers and cache (4KB each for data and instructions) are implemented as dual interlocked storage cells (DICE)

1907VM014

• 0.25 μm SOI CMOS process; manufacturing to be moved to Mikron
• 256-pin ceramic QFP
• production planned for 2016 (previously this device was planned to go into production in 2014 under the name 1907VE1T or 1907VM1T)
• radiation tolerance to not less than 200 kRad
• SoC including SpaceWire, GOST R 52070-2003 (Russian version of MIL-STD-1553), SPI, 32 GPIO, 2 UART, 3 timers, JTAG
• cache (8KB each for data and instructions)

1907VM038

• development name Skhema-10
• 0.25 μm SOI CMOS process; manufacturing to be moved to Mikron
• 675-pin ceramic BGA
• SoC including SpaceWire, GOST R 52070-2003 (MIL-STD-1553), RapidIO, SPI, I²C, 16 GPIO, 2 UART, 3 32-bit timers, JTAG, DSP (same command set as DSP in 1890VM7Ya)
• DDR2 SDRAM controller with ECC
• cache (8KB each for data and instructions)
• working temperature from -60 to 125 °C

1907VM044

• development name Obrabotka-10
• 0.25 μm SOI CMOS process; manufactured by Mikron
• 256-pin ceramic QFP
• SoC including SpaceWire, GOST R 52070-2003 (MIL-STD-1553), SPI, 32 GPIO, 2 UART, 3 timers, JTAG
• radiation tolerance to not less than 200 kRad
• triple modular redundancy in processor core
• both registers and cache (4KB each for data and instructions) are implemented as dual interlocked storage cells (DICE) with 1 parity bit per byte for cache and Hamming code for registers
• SECDED for external memory
• working temperature from -60 to 125 °C

1907VM056

• development name Skhema-23
• 0.25 μm SOI CMOS process; manufactured by Mikron
• 407-pin ceramic PGA
• SoC including 8-channel SpaceWire, GOST R 52070-2003 (MIL-STD-1553), SPI, I²C, CAN bus, 32 GPIO, 2 UART, 3 timers, JTAG
• cache (8KB each for data and instructions)

1907VM066

• development name Obrabotka-26
• 0.25 μm silicon on insulator (SOI) CMOS process; manufactured by Mikron
• 407-pin ceramic PGA
• SoC including 4-channel SpaceWire, GOST R 52070-2003 (MIL-STD-1553), SPI, I²C, RapidIO, GPIO, 2 UART, 3 timers, JTAG, PCI, co-processor for image processing
• cache (8KB each for data and instructions)

1907VK016

• development name Obrabotka-29
• 0.25 μm silicon on insulator (SOI) CMOS process; manufactured by Mikron
• PGA
• SoC including 4-channel SpaceWire, GOST R 52070-2003 (MIL-STD-1553), SPI, 32 GPIO, 2 UART, 3 timers, 128KB SRAM
• triple modular redundancy in processor core

See also

• KOMDIV-64, 64-bit MIPS processors developed by NIISI
• Mongoose-V, a 32-bit MIPS processor for spacecraft applications developed for NASA
• Soviet integrated circuit designation

References

1. "Отделение разработки вычислительных систем" [Computer systems development branch] (in Russian). Moscow: NIISI. Retrieved 9 September 2016.
2. "First Russian MIPS-Compatible Microprocessor". 22 December 2007. Retrieved 6 September 2016.
3. Шунков, Валерий (28 March 2014). "Российская микроэлектроника для космоса: кто и что производит" [Russian microelectronics for space applications: Who manufactures what] (in Russian). Geektimes. Retrieved 8 April 2017.
4. ^ "Разработка СБИС - Развитие микропроцессоров с архитектурой КОМДИВ" [VLSI development - Development of microprocessors using the KOMDIV architecture] (in Russian). Moscow: NIISI. Retrieved 6 September 2016.
5. "ОДНОКРИСТАЛЬНЫЙ МИКРОПРОЦЕССОР С АРХИТЕКТУРОЙ MIPS 1B812" [Single-chip microprocessor with MIPS architecture 1V812] (in Russian). Moscow: NIISI. Archived from the original on 21 July 2006. Retrieved 7 September 2016.
6. ^ "Изделия отечественного производства" [Domestic products] (in Russian). Moscow: AO "ENPO SPELS". Retrieved 1 September 2016.
7. ^ "Микросхемы вычислительных средств, включая микропроцессоры, микроЭВМ, цифровые процессоры обработки сигналов и контроллеры" [Integrated circuits for computing devices, including microprocessors, microcomputers, digital signal processors, and controllers] (in Russian). Promelektronika VPK. Archived from the original on 28 March 2017. Retrieved 25 October 2017.
8. ^ "Перспективные ЭВМ семейства БАГЕТ" [Future computers in the BAGET family] (PDF) (in Russian). Moscow: AO KB "Korund-M". 2017. Retrieved 1 April 2021.
9. "1890ВМ2Т" [1890VM2T] (PDF) (in Russian). Moscow: NIISI. Retrieved 9 September 2016.
10. ^ Костарев, Иван Николаевич (28 January 2017). "Методика обеспечения сбоеустойчивости ПЛИС для ракетно-космического применения" [Method for ensuring the fail-safe operation of FPGA in rocket and space applications] (in Russian). Moscow: Moscow Institute of Electronics and Mathematics. Archived from the original on 28 March 2017. Retrieved 11 February 2020.
11. ^ Osipenko, Pavel Nikolaevich (12 October 2011). "Аспекты радиационной стойкости интегральных микросхем" [Aspects of the radiation resistance of integrated circuits] (PDF) (in Russian). Moscow: NIISI. Archived from the original (PDF) on 25 April 2012. Retrieved 7 September 2016.
12. ^ Osipenko, Pavel Nikolaevich (25 May 2012). "ИЗДЕЛИЯ НАУЧНО-ИССЛЕДОВАТЕЛЬСКОГО ИНСТИТУТА СИСТЕМНЫХ ИССЛЕДОВАНИЙ РАН ДЛЯ АЭРОКОСМИЧЕСКИХ ПРИЛОЖЕНИЙ" [ELECTRONIC COMPONENTS OF SCIENTIFIC RESEARCH INSTITUTE FOR SYSTEM ANALYSIS RAS FOR SPACE APPLICATION] (PDF). Scientific experiments on small satellites: apparatus, data collection and control, electronic components (in Russian). Tarusa. pp. 139–148. ISSN 2075-6836. Retrieved 7 September 2016.
13. "Микропроцессоры и микроконтроллеры" [Microprocessors and microcontrollers] (in Russian). Nizhny Novgorod: MVC. 2014. Archived from the original on 10 March 2017. Retrieved 29 March 2018.
14. ^ Serdin, O.V. (2017). "The special radiation-hardened processors for new highly informative experiments in space". Journal of Physics: Conference Series. 798 (1): 012010. Bibcode:2017JPhCS.798a2010S. doi:10.1088/1742-6596/798/1/012010.
15. ^ Serdin, O.V. (13 October 2016). "The special radiation-hardened processors for new highly informative experiments in space" (PDF). Retrieved 5 April 2017.
16. "Микросхема 1907ВМ038" [Integrated circuit 1907VM038] (PDF) (in Russian). Moscow: NIISI. Retrieved 28 March 2017.
17. "Микросхема 1907ВМ044" [Integrated circuit 1907VM044] (PDF) (in Russian). Moscow: NIISI. Retrieved 3 April 2017.

• Radiation-hardened microprocessors
• Avionics computers
• MIPS implementations
• 32-bit microprocessors