List of ARM processors

(Redirected from List of ARM microarchitectures)

"ARM8" redirects here. For the ARMv8-A architecture, see ARMv8-A. For the ARMv8-R architecture, see ARMv8-R.

This is a list of central processing units based on the ARM family of instruction sets designed by ARM Ltd. and third parties, sorted by version of the ARM instruction set, release and name. In 2005, ARM provided a summary of the numerous vendors who implement ARM cores in their design. Keil also provides a somewhat newer summary of vendors of ARM based processors. ARM further provides a chart displaying an overview of the ARM processor lineup with performance and functionality versus capabilities for the more recent ARM core families.

Processors

Designed by ARM

Product family	ARM architecture	Processor	Feature	Cache (I / D), MMU	Typical MIPS @ MHz	Reference
ARM1	ARMv1	ARM1	First implementation	None
ARM2	ARMv2	ARM2	ARMv2 added the MUL (multiply) instruction	None	0.33 DMIPS/MHz
ARM2aS	ARMv2a	ARM250	Integrated MEMC (MMU), graphics and I/O processor. ARMv2a added the SWP and SWPB (swap) instructions	None, MEMC1a
ARM2aS	ARMv2a	ARM3	First integrated memory cache	4 KB unified	0.50 DMIPS/MHz
ARM6	ARMv3	ARM60	ARMv3 first to support 32-bit memory address space (previously 26-bit). ARMv3M first added long multiply instructions (32x32=64).	None	10 MIPS @ 12 MHz
		ARM600	As ARM60, cache and coprocessor bus (for FPA10 floating-point unit)	4 KB unified	28 MIPS @ 33 MHz
		ARM610	As ARM60, cache, no coprocessor bus	4 KB unified	17 MIPS @ 20 MHz 0.65 DMIPS/MHz
ARM7	ARMv3	ARM700	coprocessor bus (for FPA11 floating-point unit)	8 KB unified	40 MHz
		ARM710	As ARM700, no coprocessor bus	8 KB unified	40 MHz
		ARM710a	As ARM710, also used as core of ARM7100	8 KB unified	40 MHz 0.68 DMIPS/MHz
ARM7T	ARMv4T	ARM7TDMI(-S)	3-stage pipeline, Thumb, ARMv4 first to drop legacy ARM 26-bit addressing	None	15 MIPS @ 16.8 MHz 63 DMIPS @ 70 MHz
		ARM710T	As ARM7TDMI, cache	8 KB unified, MMU	36 MIPS @ 40 MHz
		ARM720T	As ARM7TDMI, cache	8 KB unified, MMU with FCSE (Fast Context Switch Extension)	60 MIPS @ 59.8 MHz
		ARM740T	As ARM7TDMI, cache	MPU
ARM7EJ	ARMv5TEJ	ARM7EJ-S	5-stage pipeline, Thumb, Jazelle DBX, enhanced DSP instructions	None
ARM8	ARMv4	ARM810	5-stage pipeline, static branch prediction, double-bandwidth memory	8 KB unified, MMU	84 MIPS @ 72 MHz 1.16 DMIPS/MHz
ARM9T	ARMv4T	ARM9TDMI	5-stage pipeline, Thumb	None
		ARM920T	As ARM9TDMI, cache	16 KB / 16 KB, MMU with FCSE (Fast Context Switch Extension)	200 MIPS @ 180 MHz
		ARM922T	As ARM9TDMI, caches	8 KB / 8 KB, MMU
		ARM940T	As ARM9TDMI, caches	4 KB / 4 KB, MPU
ARM9E	ARMv5TE	ARM946E-S	Thumb, enhanced DSP instructions, caches	Variable, tightly coupled memories, MPU
		ARM966E-S	Thumb, enhanced DSP instructions	No cache, TCMs
		ARM968E-S	As ARM966E-S	No cache, TCMs
	ARMv5TEJ	ARM926EJ-S	Thumb, Jazelle DBX, enhanced DSP instructions	Variable, TCMs, MMU	220 MIPS @ 200 MHz
	ARMv5TE	ARM996HS	Clockless processor, as ARM966E-S	No caches, TCMs, MPU
ARM10E	ARMv5TE	ARM1020E	6-stage pipeline, Thumb, enhanced DSP instructions, (VFP)	32 KB / 32 KB, MMU
	ARMv5TE	ARM1022E	As ARM1020E	16 KB / 16 KB, MMU
	ARMv5TEJ	ARM1026EJ-S	Thumb, Jazelle DBX, enhanced DSP instructions, (VFP)	Variable, MMU or MPU
ARM11	ARMv6	ARM1136J(F)-S	8-stage pipeline, SIMD, Thumb, Jazelle DBX, (VFP), enhanced DSP instructions, unaligned memory access	Variable, MMU	740 @ 532–665 MHz (i.MX31 SoC), 400–528 MHz
	ARMv6T2	ARM1156T2(F)-S	9-stage pipeline, SIMD, Thumb-2, (VFP), enhanced DSP instructions	Variable, MPU
	ARMv6Z	ARM1176JZ(F)-S	As ARM1136EJ(F)-S	Variable, MMU + TrustZone	965 DMIPS @ 772 MHz, up to 2,600 DMIPS with four processors
	ARMv6K	ARM11MPCore	As ARM1136EJ(F)-S, 1–4 core SMP	Variable, MMU
SecurCore	ARMv6-M	SC000	As Cortex-M0		0.9 DMIPS/MHz
	ARMv4T	SC100	As ARM7TDMI
	ARMv7-M	SC300	As Cortex-M3		1.25 DMIPS/MHz
Cortex-M	ARMv6-M	Cortex-M0	Microcontroller profile, most Thumb + some Thumb-2, hardware multiply instruction (optional small), optional system timer, optional bit-banding memory	Optional cache, no TCM, no MPU	0.84 DMIPS/MHz
		Cortex-M0+	Microcontroller profile, most Thumb + some Thumb-2, hardware multiply instruction (optional small), optional system timer, optional bit-banding memory	Optional cache, no TCM, optional MPU with 8 regions	0.93 DMIPS/MHz
		Cortex-M1	Microcontroller profile, most Thumb + some Thumb-2, hardware multiply instruction (optional small), OS option adds SVC / banked stack pointer, optional system timer, no bit-banding memory	Optional cache, 0–1024 KB I-TCM, 0–1024 KB D-TCM, no MPU	136 DMIPS @ 170 MHz, (0.8 DMIPS/MHz FPGA-dependent)
	ARMv7-M	Cortex-M3	Microcontroller profile, Thumb / Thumb-2, hardware multiply and divide instructions, optional bit-banding memory	Optional cache, no TCM, optional MPU with 8 regions	1.25 DMIPS/MHz
	ARMv7E-M	Cortex-M4	Microcontroller profile, Thumb / Thumb-2 / DSP / optional VFPv4-SP single-precision FPU, hardware multiply and divide instructions, optional bit-banding memory	Optional cache, no TCM, optional MPU with 8 regions	1.25 DMIPS/MHz (1.27 w/FPU)
	ARMv7E-M	Cortex-M7	Microcontroller profile, Thumb / Thumb-2 / DSP / optional VFPv5 single and double precision FPU, hardware multiply and divide instructions	0−64 KB I-cache, 0−64 KB D-cache, 0–16 MB I-TCM, 0–16 MB D-TCM (all these w/optional ECC), optional MPU with 8 or 16 regions	2.14 DMIPS/MHz
	ARMv8-M Baseline	Cortex-M23	Microcontroller profile, Thumb-1 (most), Thumb-2 (some), Divide, TrustZone	Optional cache, no TCM, optional MPU with 16 regions	1.03 DMIPS/MHz
	ARMv8-M Mainline	Cortex-M33	Microcontroller profile, Thumb-1, Thumb-2, Saturated, DSP, Divide, FPU (SP), TrustZone, Co-processor	Optional cache, no TCM, optional MPU with 16 regions	1.50 DMIPS/MHz
	ARMv8-M Mainline	Cortex-M35P	Microcontroller profile, Thumb-1, Thumb-2, Saturated, DSP, Divide, FPU (SP), TrustZone, Co-processor	Built-in cache (with option 2–16 KB), I-cache, no TCM, optional MPU with 16 regions	1.50 DMIPS/MHz
	ARMv8.1-M Mainline	Cortex-M52			1.60 DMIPS/MHz
		Cortex-M55			1.69 DMIPS/MHz
		Cortex-M85			3.13 DMIPS/MHz
Cortex-R	ARMv7-R	Cortex-R4	Real-time profile, Thumb / Thumb-2 / DSP / optional VFPv3 FPU, hardware multiply and optional divide instructions, optional parity & ECC for internal buses / cache / TCM, 8-stage pipeline dual-core running lockstep with fault logic	0–64 KB / 0–64 KB, 0–2 of 0–8 MB TCM, opt. MPU with 8/12 regions	1.67 DMIPS/MHz
		Cortex-R5	Real-time profile, Thumb / Thumb-2 / DSP / optional VFPv3 FPU and precision, hardware multiply and optional divide instructions, optional parity & ECC for internal buses / cache / TCM, 8-stage pipeline dual-core running lock-step with fault logic / optional as 2 independent cores, low-latency peripheral port (LLPP), accelerator coherency port (ACP)	0–64 KB / 0–64 KB, 0–2 of 0–8 MB TCM, opt. MPU with 12/16 regions	1.67 DMIPS/MHz
		Cortex-R7	Real-time profile, Thumb / Thumb-2 / DSP / optional VFPv3 FPU and precision, hardware multiply and optional divide instructions, optional parity & ECC for internal buses / cache / TCM, 11-stage pipeline dual-core running lock-step with fault logic / out-of-order execution / dynamic register renaming / optional as 2 independent cores, low-latency peripheral port (LLPP), ACP	0–64 KB / 0–64 KB, ? of 0–128 KB TCM, opt. MPU with 16 regions	2.50 DMIPS/MHz
		Cortex-R8	TBD	0–64 KB / 0–64 KB L1, 0–1 / 0–1 MB TCM, opt MPU with 24 regions	2.50 DMIPS/MHz
	ARMv8-R	Cortex-R52	TBD	0–32 KB / 0–32 KB L1, 0–1 / 0–1 MB TCM, opt MPU with 24+24 regions	2.09 DMIPS/MHz
		Cortex-R52+	TBD	0–32 KB / 0–32 KB L1, 0–1 / 0–1 MB TCM, opt MPU with 24+24 regions	2.09 DMIPS/MHz
		Cortex-R82	TBD	16–128 KB /16–64 KB L1, 64K–1MB L2, 0.16–1 / 0.16–1 MB TCM, opt MPU with 32+32 regions	3.41 DMIPS/MHz
Cortex-A (32-bit)	ARMv7-A	Cortex-A5	Application profile, ARM / Thumb / Thumb-2 / DSP / SIMD / Optional VFPv4-D16 FPU / Optional NEON / Jazelle RCT and DBX, 1–4 cores / optional MPCore, snoop control unit (SCU), generic interrupt controller (GIC), accelerator coherence port (ACP)	4−64 KB / 4−64 KB L1, MMU + TrustZone	1.57 DMIPS/MHz per core
		Cortex-A7	Application profile, ARM / Thumb / Thumb-2 / DSP / VFPv4 FPU / NEON / Jazelle RCT and DBX / Hardware virtualization, in-order execution, superscalar, 1–4 SMP cores, MPCore, Large Physical Address Extensions (LPAE), snoop control unit (SCU), generic interrupt controller (GIC), architecture and feature set are identical to A15, 8–10 stage pipeline, low-power design	8−64 KB / 8−64 KB L1, 0–1 MB L2, MMU + TrustZone	1.9 DMIPS/MHz per core
		Cortex-A8	Application profile, ARM / Thumb / Thumb-2 / VFPv3 FPU / NEON / Jazelle RCT and DAC, 13-stage superscalar pipeline	16–32 KB / 16–32 KB L1, 0–1 MB L2 opt. ECC, MMU + TrustZone	Up to 2000 (2.0 DMIPS/MHz in speed from 600 MHz to greater than 1 GHz)
		Cortex-A9	Application profile, ARM / Thumb / Thumb-2 / DSP / Optional VFPv3 FPU / Optional NEON / Jazelle RCT and DBX, out-of-order speculative issue superscalar, 1–4 SMP cores, MPCore, snoop control unit (SCU), generic interrupt controller (GIC), accelerator coherence port (ACP)	16–64 KB / 16–64 KB L1, 0–8 MB L2 opt. parity, MMU + TrustZone	2.5 DMIPS/MHz per core, 10,000 DMIPS @ 2 GHz on Performance Optimized TSMC 40G (dual-core)
		Cortex-A12	Application profile, ARM / Thumb-2 / DSP / VFPv4 FPU / NEON / Hardware virtualization, out-of-order speculative issue superscalar, 1–4 SMP cores, Large Physical Address Extensions (LPAE), snoop control unit (SCU), generic interrupt controller (GIC), accelerator coherence port (ACP)	32−64 KB	3.0 DMIPS/MHz per core
		Cortex-A15	Application profile, ARM / Thumb / Thumb-2 / DSP / VFPv4 FPU / NEON / integer divide / fused MAC / Jazelle RCT / hardware virtualization, out-of-order speculative issue superscalar, 1–4 SMP cores, MPCore, Large Physical Address Extensions (LPAE), snoop control unit (SCU), generic interrupt controller (GIC), ACP, 15-24 stage pipeline	32 KB w/parity / 32 KB w/ECC L1, 0–4 MB L2, L2 has ECC, MMU + TrustZone	At least 3.5 DMIPS/MHz per core (up to 4.01 DMIPS/MHz depending on implementation)
		Cortex-A17	Application profile, ARM / Thumb / Thumb-2 / DSP / VFPv4 FPU / NEON / integer divide / fused MAC / Jazelle RCT / hardware virtualization, out-of-order speculative issue superscalar, 1–4 SMP cores, MPCore, Large Physical Address Extensions (LPAE), snoop control unit (SCU), generic interrupt controller (GIC), ACP	32 KB L1, 256 KB–8 MB L2 w/optional ECC	2.8 DMIPS/MHz
	ARMv8-A	Cortex-A32	Application profile, AArch32, 1–4 SMP cores, TrustZone, NEON advanced SIMD, VFPv4, hardware virtualization, dual issue, in-order pipeline	8–64 KB w/optional parity / 8−64 KB w/optional ECC L1 per core, 128 KB–1 MB L2 w/optional ECC shared
Cortex-A (64-bit)	ARMv8-A	Cortex-A34	Application profile, AArch64, 1–4 SMP cores, TrustZone, NEON advanced SIMD, VFPv4, hardware virtualization, 2-width decode, in-order pipeline	8−64 KB w/parity / 8−64 KB w/ECC L1 per core, 128 KB–1 MB L2 shared, 40-bit physical addresses
		Cortex-A35	Application profile, AArch32 and AArch64, 1–4 SMP cores, TrustZone, NEON advanced SIMD, VFPv4, hardware virtualization, 2-width decode, in-order pipeline	8−64 KB w/parity / 8−64 KB w/ECC L1 per core, 128 KB–1 MB L2 shared, 40-bit physical addresses	1.78 DMIPS/MHz
		Cortex-A53	Application profile, AArch32 and AArch64, 1–4 SMP cores, TrustZone, NEON advanced SIMD, VFPv4, hardware virtualization, 2-width decode, in-order pipeline	8−64 KB w/parity / 8−64 KB w/ECC L1 per core, 128 KB–2 MB L2 shared, 40-bit physical addresses	2.3 DMIPS/MHz
		Cortex-A57	Application profile, AArch32 and AArch64, 1–4 SMP cores, TrustZone, NEON advanced SIMD, VFPv4, hardware virtualization, 3-width decode superscalar, deeply out-of-order pipeline	48 KB w/DED parity / 32 KB w/ECC L1 per core; 512 KB–2 MB L2 shared w/ECC; 44-bit physical addresses	4.1–4.8 DMIPS/MHz
		Cortex-A72	Application profile, AArch32 and AArch64, 1–4 SMP cores, TrustZone, NEON advanced SIMD, VFPv4, hardware virtualization, 3-width superscalar, deeply out-of-order pipeline	48 KB w/DED parity / 32 KB w/ECC L1 per core; 512 KB–2 MB L2 shared w/ECC; 44-bit physical addresses	6.3-7.3 DMIPS/MHz
		Cortex-A73	Application profile, AArch32 and AArch64, 1–4 SMP cores, TrustZone, NEON advanced SIMD, VFPv4, hardware virtualization, 2-width superscalar, deeply out-of-order pipeline	64 KB / 32−64 KB L1 per core, 256 KB–8 MB L2 shared w/ optional ECC, 44-bit physical addresses	7.4-8.5 DMIPS/MHz
	ARMv8.2-A	Cortex-A55	Application profile, AArch32 and AArch64, 1–8 SMP cores, TrustZone, NEON advanced SIMD, VFPv4, hardware virtualization, 2-width decode, in-order pipeline	16−64 KB / 16−64 KB L1, 256 KB L2 per core, 4 MB L3 shared	3 DMIPS/MHz
		Cortex-A65	Application profile, AArch64, 1–8 SMP cores, TrustZone, NEON advanced SIMD, VFPv4, hardware virtualization, 2-wide decode superscalar, 3-width issue, out-of-order pipeline, SMT
		Cortex-A65AE	As ARM Cortex-A65, adds dual core lockstep for safety applications	64 / 64 KB L1, 256 KB L2 per core, 4 MB L3 shared
		Cortex-A75	Application profile, AArch32 and AArch64, 1–8 SMP cores, TrustZone, NEON advanced SIMD, VFPv4, hardware virtualization, 3-width decode superscalar, deeply out-of-order pipeline	64 / 64 KB L1, 512 KB L2 per core, 4 MB L3 shared	8.2-9.5 DMIPS/MHz
		Cortex-A76	Application profile, AArch32 (non-privileged level or EL0 only) and AArch64, 1–4 SMP cores, TrustZone, NEON advanced SIMD, VFPv4, hardware virtualization, 4-width decode superscalar, 8-way issue, 13 stage pipeline, deeply out-of-order pipeline	64 / 64 KB L1, 256−512 KB L2 per core, 512 KB−4 MB L3 shared	10.7-12.4 DMIPS/MHz
		Cortex-A76AE	As ARM Cortex-A76, adds dual core lockstep for safety applications
		Cortex-A77	Application profile, AArch32 (non-privileged level or EL0 only) and AArch64, 1–4 SMP cores, TrustZone, NEON advanced SIMD, VFPv4, hardware virtualization, 4-width decode superscalar, 6-width instruction fetch, 12-way issue, 13 stage pipeline, deeply out-of-order pipeline	1.5K L0 MOPs cache, 64 / 64 KB L1, 256−512 KB L2 per core, 512 KB−4 MB L3 shared	13-16 DMIPS/MHz
		Cortex-A78
		Cortex-A78AE	As ARM Cortex-A78, adds dual core lockstep for safety applications
		Cortex-A78C
	ARMv9-A	Cortex-A510
		Cortex-A710
		Cortex-A715
	ARMv9.2-A	Cortex-A520
		Cortex-A720
		Cortex-A725
Cortex-X	ARMv8.2-A	Cortex-X1	Performance-tuned variant of Cortex-A78
	ARMv9-A	Cortex-X2		64 / 64 KB L1, 512–1024 KiB L2 per core, 512 KiB–8 MiB L3 shared
	ARMv9-A	Cortex-X3		64 / 64 KB L1, 512–2048 KiB L2 per core, 512 KiB–16 MiB L3 shared
	ARMv9.2-A	Cortex-X4		64 / 64 KB L1, 512–2048 KiB L2 per core, 512 KiB–32 MiB L3 shared
	ARMv9.2-A	Cortex-X925
Neoverse	ARMv8.2-A	Neoverse N1	Application profile, AArch32 (non-privileged level or EL0 only) and AArch64, 1–4 SMP cores, TrustZone, NEON advanced SIMD, VFPv4, hardware virtualization, 4-width decode superscalar, 8-way dispatch/issue, 13 stage pipeline, deeply out-of-order pipeline	64 / 64 KB L1, 512−1024 KB L2 per core, 2−128 MB L3 shared, 128 MB system level cache
	ARMv8.2-A	Neoverse E1	Application profile, AArch64, 1–8 SMP cores, TrustZone, NEON advanced SIMD, VFPv4, hardware virtualization, 2-wide decode superscalar, 3-width issue, 10 stage pipeline, out-of-order pipeline, SMT	32−64 KB / 32−64 KB L1, 256 KB L2 per core, 4 MB L3 shared
	ARMv8.4-A	Neoverse V1
	ARMv9-A	Neoverse N2
	ARMv9-A	Neoverse V2
	ARMv9.2-A	Neoverse N3
	ARMv9.2-A	Neoverse V3
ARM family	ARM architecture	ARM core	Feature	Cache (I / D), MMU	Typical MIPS @ MHz	Reference

Designed by third parties

These cores implement the ARM instruction set, and were developed independently by companies with an architectural license from ARM.

Product family	ARM architecture	Processor	Feature	Cache (I / D), MMU	Typical MIPS @ MHz
StrongARM (Digital)	ARMv4	SA-110	5-stage pipeline	16 KB / 16 KB, MMU	100–233 MHz 1.0 DMIPS/MHz
StrongARM (Digital)	ARMv4	SA-1100	derivative of the SA-110	16 KB / 8 KB, MMU
Faraday (Faraday Technology)	ARMv4	FA510	6-stage pipeline	Up to 32 KB / 32 KB cache, MPU	1.26 DMIPS/MHz 100–200 MHz
		FA526	6-stage pipeline	Up to 32 KB / 32 KB cache, MMU	1.26 MIPS/MHz 166–300 MHz
		FA626	8-stage pipeline	32 KB / 32 KB cache, MMU	1.35 DMIPS/MHz 500 MHz
	ARMv5TE	FA606TE	5-stage pipeline	No cache, no MMU	1.22 DMIPS/MHz 200 MHz
		FA626TE	8-stage pipeline	32 KB / 32 KB cache, MMU	1.43 MIPS/MHz 800 MHz
		FMP626TE	8-stage pipeline, SMP		1.43 MIPS/MHz 500 MHz
		FA726TE	13 stage pipeline, dual issue		2.4 DMIPS/MHz 1000 MHz
XScale (Intel / Marvell)	ARMv5TE	XScale	7-stage pipeline, Thumb, enhanced DSP instructions	32 KB / 32 KB, MMU	133–400 MHz
		Bulverde	Wireless MMX, wireless SpeedStep added	32 KB / 32 KB, MMU	312–624 MHz
		Monahans	Wireless MMX2 added	32 KB / 32 KB L1, optional L2 cache up to 512 KB, MMU	Up to 1.25 GHz
Sheeva (Marvell)	ARMv5	Feroceon	5–8 stage pipeline, single-issue	16 KB / 16 KB, MMU	600–2000 MHz
		Jolteon	5–8 stage pipeline, dual-issue	32 KB / 32 KB, MMU	600–2000 MHz
		PJ1 (Mohawk)	5–8 stage pipeline, single-issue, Wireless MMX2	32 KB / 32 KB, MMU	1.46 DMIPS/MHz 1.06 GHz
	ARMv6 / ARMv7-A	PJ4	6–9 stage pipeline, dual-issue, Wireless MMX2, SMP	32 KB / 32 KB, MMU	2.41 DMIPS/MHz 1.6 GHz
Snapdragon (Qualcomm)	ARMv7-A	Scorpion	1 or 2 cores. ARM / Thumb / Thumb-2 / DSP / SIMD / VFPv3 FPU / NEON (128-bit wide)	256 KB L2 per core	2.1 DMIPS/MHz per core
	ARMv7-A	Krait	1, 2, or 4 cores. ARM / Thumb / Thumb-2 / DSP / SIMD / VFPv4 FPU / NEON (128-bit wide)	4 KB / 4 KB L0, 16 KB / 16 KB L1, 512 KB L2 per core	3.3 DMIPS/MHz per core
	ARMv8-A	Kryo	4 cores.	?	Up to 2.2 GHz (6.3 DMIPS/MHz)
A series (Apple)	ARMv7-A	Swift	2 cores. ARM / Thumb / Thumb-2 / DSP / SIMD / VFPv4 FPU / NEON	L1: 32 KB / 32 KB, L2: 1 MB shared	3.5 DMIPS/MHz per core
	ARMv8-A	Cyclone	2 cores. ARM / Thumb / Thumb-2 / DSP / SIMD / VFPv4 FPU / NEON / TrustZone / AArch64. Out-of-order, superscalar.	L1: 64 KB / 64 KB, L2: 1 MB shared SLC: 4 MB	1.3 or 1.4 GHz
	ARMv8-A	Typhoon	2 or 3 cores. ARM / Thumb / Thumb-2 / DSP / SIMD / VFPv4 FPU / NEON / TrustZone / AArch64	L1: 64 KB / 64 KB, L2: 1 MB or 2 MB shared SLC: 4 MB	1.4 or 1.5 GHz
	ARMv8-A	Twister	2 cores. ARM / Thumb / Thumb-2 / DSP / SIMD / VFPv4 FPU / NEON / TrustZone / AArch64	L1: 64 KB / 64 KB, L2: 2 MB shared SLC: 4 MB or 0 MB	1.85 or 2.26 GHz
	ARMv8-A	Hurricane and Zephyr	Hurricane: 2 or 3 cores. AArch64, out-of-order, superscalar, 6-decode, 6-issue, 9-wide Zephyr: 2 or 3 cores. AArch64, out-of-order, superscalar.	L1: 64 KB / 64 KB, L2: 3 MB or 8 MB shared L1: 32 KB / 32 KB. L2: none SLC: 4 MB or 0 MB	2.34 or 2.38 GHz 1.05 GHz
	ARMv8.2-A	Monsoon and Mistral	Monsoon: 2 cores. AArch64, out-of-order, superscalar, 7-decode, ?-issue, 11-wide Mistral: 4 cores. AArch64, out-of-order, superscalar. Based on Swift.	L1I: 128 KB, L1D: 64 KB, L2: 8 MB shared L1: 32 KB / 32 KB, L2: 1 MB shared SLC: 4 MB	2.39 GHz 1.70 GHz
	ARMv8.3-A	Vortex and Tempest	Vortex: 2 or 4 cores. AArch64, out-of-order, superscalar, 7-decode, ?-issue, 11-wide Tempest: 4 cores. AArch64, out-of-order, superscalar, 3-decode. Based on Swift.	L1: 128 KB / 128 KB, L2: 8 MB shared L1: 32 KB / 32 KB, L2: 2 MB shared SLC: 8 MB	2.49 GHz 1.59 GHz
	ARMv8.4-A	Lightning and Thunder	Lightning: 2 cores. AArch64, out-of-order, superscalar, 7-decode, ?-issue, 11-wide Thunder: 4 cores. AArch64, out-of-order, superscalar.	L1: 128 KB / 128 KB, L2: 8 MB shared L1: 32 KB / 48 KB, L2: 4 MB shared SLC: 16 MB	2.66 GHz 1.73 GHz
	ARMv8.5-A	Firestorm and Icestorm	Firestorm: 2 cores. AArch64, out-of-order, superscalar, 8-decode, ?-issue, 14-wide Icestorm: 4 cores. AArch64, out-of-order, superscalar, 4-decode, ?-issue, 7-wide.	L1: 192 KB / 128 KB, L2: 8 MB shared L1: 128 KB / 64 KB, L2: 4 MB shared SLC: 16 MB	3.0 GHz 1.82 GHz
	ARMv8.6-A	Avalanche and Blizzard	Avalanche: 2 cores. AArch64, out-of-order, superscalar, 8-decode, ?-issue, 14-wide Blizzard: 4 cores. AArch64, out-of-order, superscalar, 4-decode, ?-issue, 8-wide.	L1: 192 KB / 128 KB, L2: 12 MB shared L1: 128 KB / 64 KB, L2: 4 MB shared SLC: 32 MB	2.93 or 3.23 GHz 2.02 GHz
	ARMv8.6-A	Everest and Sawtooth	Everest: 2 cores. AArch64, out-of-order, superscalar, 8-decode, ?-issue, 14-wide Sawtooth: 4 cores. AArch64, out-of-order, superscalar, 4-decode, ?-issue, 8-wide.	L1: 192 KB / 128 KB, L2: 16 MB shared L1: 128 KB / 64 KB, L2: 4 MB shared SLC: 24 MB	3.46 GHz 2.02 GHz
	ARMv8.6-A	Apple A17 Pro	Apple A17 Pro (P-cores): 2 cores. AArch64, out-of-order, superscalar, 8-decode, ?-issue, 14-wide Apple A17 Pro (E-cores): 4 cores. AArch64, out-of-order, superscalar, 4-decode, ?-issue, 8-wide.	L1: 192 KB / 128 KB, L2: 16 MB shared L1: 128 KB / 64 KB, L2: 4 MB shared SLC: 24 MB	3.78 GHz 2.11 GHz
M series (Apple)	ARMv8.5-A	Firestorm and Icestorm	Firestorm: 4, 6, 8 or 16 cores. AArch64, out-of-order, superscalar, 8-decode, ?-issue, 14-wide Icestorm: 2 or 4 cores. AArch64, out-of-order, superscalar, 4-decode, ?-issue, 7-wide.	L1: 192 KB / 128 KB, L2: 12, 24 or 48 MB shared L1: 128 KB / 64 KB, L2: 4 or 8 MB shared SLC: 8, 24, 48 or 96 MB	3.2-3.23 GHz 2.06 GHz
	ARMv8.6-A	Avalanche and Blizzard	Avalanche: 4, 6, 8 or 16 cores. AArch64, out-of-order, superscalar, 8-decode, ?-issue, 14-wide Blizzard: 4 or 8 cores. AArch64, out-of-order, superscalar, 4-decode, ?-issue, 8-wide.	L1: 192 KB / 128 KB, L2: 16, 32 or 64 MB shared L1: 128 KB / 64 KB, L2: 4 or 8 MB shared SLC: 8, 24, 48 or 96 MB	3.49 GHz 2.42 GHz
	ARMv8.6-A	Apple M3	Apple M3 (P-cores): 4, 5, 6, 10, 12 or 16 cores. AArch64, out-of-order, superscalar, 8-decode, ?-issue, 14-wide Apple M3 (E-cores): 4 or 6 cores. AArch64, out-of-order, superscalar, 4-decode, ?-issue, 8-wide.	L1: 192 KB / 128 KB, L2: 16, 32 or 64 MB shared L1: 128 KB / 64 KB, L2: 4 or 8 MB shared SLC: 8, 24, 48 or 96 MB	4.05 GHz 2.75 GHz
	ARMv9.2-A	Apple M4	Apple M4 (P-cores): 3 or 4 cores. AArch64, out-of-order, superscalar, 8-decode, ?-issue, 14-wide Apple M4 (E-cores): 6 cores. AArch64, out-of-order, superscalar, 4-decode, ?-issue, 8-wide.	L1: 192 KB / 128 KB, L2: 16, 32 or 64 MB shared L1: 128 KB / 64 KB, L2: 4 or 8 MB shared SLC: 8, 24, 48 or 96 MB	4.40 GHz 2.85 GHz
X-Gene (Applied Micro)	ARMv8-A	X-Gene	64-bit, quad issue, SMP, 64 cores	Cache, MMU, virtualization	3 GHz (4.2 DMIPS/MHz per core)
Denver (Nvidia)	ARMv8-A	Denver	2 cores. AArch64, 7-wide superscalar, in-order, dynamic code optimization, 128 MB optimization cache, Denver1: 28 nm, Denver2:16 nm	128 KB I-cache / 64 KB D-cache	Up to 2.5 GHz
Carmel (Nvidia)	ARMv8.2-A	Carmel	2 cores. AArch64, 10-wide superscalar, in-order, dynamic code optimization, ? MB optimization cache, functional safety, dual execution, parity & ECC	? KB I-cache / ? KB D-cache	Up to ? GHz
ThunderX (Cavium)	ARMv8-A	ThunderX	64-bit, with two models with 8–16 or 24–48 cores (×2 w/two chips)	?	Up to 2.2 GHz
K12 (AMD)	ARMv8-A	K12	?	?	?
Exynos (Samsung)	ARMv8-A	M1 ("Mongoose")	4 cores. AArch64, 4-wide, quad-issue, superscalar, out-of-order	64 KB I-cache / 32 KB D-cache, L2: 16-way shared 2 MB	5.1 DMIPS/MHz (2.6 GHz)
	ARMv8-A	M2 ("Mongoose")	4 cores. AArch64, 4-wide, quad-issue, superscalar, out-of-order	64 KB I-cache / 32 KB D-cache, L2: 16-way shared 2 MB	2.3 GHz
	ARMv8-A	M3 ("Meerkat")	4 cores, AArch64, 6-decode, 6-issue, 6-wide. superscalar, out-of-order	64 KB I-cache / 64 KB D-cache, L2: 8-way private 512 KB, L3: 16-way shared 4 MB	2.7 GHz
	ARMv8.2-A	M4 ("Cheetah")	2 cores, AArch64, 6-decode, 6-issue, 6-wide. superscalar, out-of-order	64 KB I-cache / 64 KB D-cache, L2: 8-way private 1 MB, L3: 16-way shared 3 MB	2.73 GHz
	ARMv8.2-A	M5 ("Lion")	2 cores, AArch64, 6-decode, 6-issue, 6-wide. superscalar, out-of-order	64 KB I-cache / 64 KB D-cache, L2: 8-way shared 2 MB, L3: 12-way shared 3 MB	2.73 GHz

Timeline

The following table lists each core by the year it was announced.

Year	Classic cores						Cortex cores				Neoverse cores
Year	ARM1-6	ARM7	ARM8	ARM9	ARM10	ARM11	Microcontroller	Real-time	Application (32-bit)	Application (64-bit)	Application (64-bit)
1985	ARM1
1986	ARM2
1989	ARM3
1992	ARM250
1993	ARM60 ARM610	ARM700
1994		ARM710 ARM7DI ARM7TDMI
1995		ARM710a
1996			ARM810
1997		ARM710T ARM720T ARM740T
1998				ARM9TDMI ARM940T
1999				ARM9E-S ARM966E-S
2000				ARM920T ARM922T ARM946E-S	ARM1020T
2001		ARM7TDMI-S ARM7EJ-S		ARM9EJ-S ARM926EJ-S	ARM1020E ARM1022E
2002					ARM1026EJ-S	ARM1136J(F)-S
2003				ARM968E-S		ARM1156T2(F)-S ARM1176JZ(F)-S
2004							Cortex-M3
2005						ARM11MPCore			Cortex-A8
2006				ARM996HS
2007							Cortex-M1		Cortex-A9
2008
2009							Cortex-M0		Cortex-A5
2010							Cortex-M4(F)		Cortex-A15
2011								Cortex-R4 Cortex-R5 Cortex-R7	Cortex-A7
2012							Cortex-M0+			Cortex-A53 Cortex-A57
2013									Cortex-A12
2014							Cortex-M7(F)		Cortex-A17
2015										Cortex-A35 Cortex-A72
2016							Cortex-M23 Cortex-M33(F)	Cortex-R8 Cortex-R52	Cortex-A32	Cortex-A73
2017										Cortex-A55 Cortex-A75
2018							Cortex-M35P(F)			Cortex-A65AE Cortex-A76 Cortex-A76AE
2019										Cortex-A77	Neoverse E1 Neoverse N1
2020							Cortex-M55(F)	Cortex-R82		Cortex-A78 Cortex-X1	Neoverse V1
2021										Cortex-A510 Cortex-A710 Cortex-X2	Neoverse N2
2022							Cortex-M85(F)	Cortex-R52+		Cortex-A715 Cortex-X3
2023							Cortex-M52(F)			Cortex-A520 Cortex-A720 Cortex-X4
2024								Cortex-R82AE		Cortex-A520AE Cortex-A720AE Cortex-A725 Cortex-X925	Neoverse N3 Neoverse V3 Neoverse V3AE

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Cortex-A5	Actions ATM702x Amlogic M805/S805, T82x Atmel SAMA5D3 InfoTM iMAPx820, iMAPx15 Qualcomm Snapdragon S4 Play, 200 RDA RDA8810PL Telechips TCC892x
Cortex-A7	Allwinner A2x, A3x, A83T, H3, H8 NXP i.MX7, QorIQ LS10xx, NXP i.MX6UL Broadcom VideoCore BCM2836, BCM23550 Leadcore LC1813, LC1860/C, LC1913, LC1960 Marvell Armada PXA1920, 1500 mini plus MediaTek MT65xx Qualcomm Snapdragon 200, 205, 208, 210, 212, 400
Cortex-A8	Allwinner A1x Apple A4 Freescale i.MX5 Rockchip RK291x Samsung Exynos 3110(S5PC110), S5PV210 Texas Instruments OMAP 3 Texas Instruments Sitara AM3xxx Texas Instruments DM38x ZiiLABS ZMS-08
Cortex-A9	Actions ATM702x, ATM703x Altera Cyclone V, Arria V/10 Amlogic AML8726, MX, M6x, M801, M802/S802, S812, T86x Apple A5, A5X Broadcom VideoCore BCM21xxx, BCM28xxx Freescale i.MX6 HiSilicon K3V2, 910's InfoTM iMAPx912 Leadcore LC1810, LC1811 Marvell Armada 1500 mini MediaTek MT65xx Nvidia Tegra, 2, 3, 4i Nufront NuSmart 2816M, NS115, NS115M Renesas EMMA EV2, R-Car H1, RZ/A Rockchip RK292x, RK30xx, RK31xx Samsung Exynos 4 421x, 441x ST-Ericsson NovaThor Telechips TCC8803 Texas Instruments OMAP 4 Texas Instruments Sitara AM4xxx VIA WonderMedia WM88x0, 89x0 Xilinx Zynq-7000 ZiiLABS ZMS-20, ZMS-40
Cortex-A15	Allwinner A80 HiSilicon K3V3 MediaTek MT8135/V Nvidia Tegra 4, K1 Renesas R-Car H2 Samsung Exynos 5 52xx, 54xx Texas Instruments OMAP 5, DRA7xx, AM57xx Texas Instruments Sitara AM5xxx
Cortex-A17	MediaTek MT6595, MT5595 MStar 6A928 Rockchip RK3288
Others	Cortex-A12
ARMv7-A compatible	Apple A6, A6X, S1, S1P, S2, S3 Broadcom Brahma-B15 Marvell P4J Qualcomm Snapdragon S1, S2, S3, S4 Plus, S4 Pro, 600, 800 (Scorpion, Krait)

ARMv8-A

Others	Cortex-A32

Application
processors
(64-bit)

ARMv8-A

Cortex-A35	NXP i.MX8X MediaTek MT6799, MT8516 Rockchip RK3308
Cortex-A53	Actions GT7, S900, V700 Allwinner A64, H5, H64, R18 Altera Stratix 10 Amlogic S9 Family, T96x Broadcom BCM2837 EZchip TILE-Mx100 HiSilicon Kirin 620, 650, 655, 658, 659, 930, 935 Marvell Armada PXA1928, Mobile PXA1908/PXA1936 MediaTek MT673x, MT675x, MT6761V, MT6762/V, MT6763T, MT6765/G/H, MT6795, MT8161, MT8163, MT8165, MT8732, MT8735, MT8752 NXP ARM S32, QorIQ LS1088, LS1043, i.MX8M Qualcomm Snapdragon 215, 410, 412, 415, 425, 427, 429, 430, 435, 439, 450, 610, 615, 616, 617, 625, 626, 630 Renesas RZ/V2M Rockchip RK3328, RK3368 Samsung Exynos 7570, 7578, 7580, 7870, 7880 Texas Instruments Sitara AM6xxx UNISOC SC9820E, SC9832E, SC9860/GV Xilinx ZynqMP
Cortex-A57	AMD Opteron A1100-series NXP QorIQ LS20xx Nvidia Tegra X1 and Tegra X2 Qualcomm Snapdragon 808 and 810 Samsung Exynos 7 5433, 7420 HiSilicon Kirin Hi1610 and Hi1612
Cortex-A72	AWS Graviton Broadcom BCM2711 HiSilicon Kirin 950, 955, Kunpeng 916 MediaTek MT6797/D/T/X, MT8173, MT8176, MT8693 MStar 6A938 Qualcomm Snapdragon 650, 652, 653 Rockchip RK3399 NXP QorIQ LS2088, QorIQ LS1046A, QorIQ LX2160A, QorIQ LS1028A, i.MX8
Cortex-A73	Qualcomm Snapdragon 460, 632, 636, 660, 662, 665, 680, 685, 6s 4G Gen 1, 835 Samsung Exynos 7872, 7884, 7885, 7904, 9609, 9610, 9611 HiSilicon Kirin 710, 960, 970 MediaTek MT6771/V, MT6799, MT8183, MT8788 Amlogic S922X
Others	Cortex-A34
ARMv8-A compatible	Ampere eMAG Apple A7, A8, A8X, A9, A9X, A10, A10X Applied Micro X-Gene Cavium ThunderX Nvidia Tegra K1 (Denver), Tegra X2 (Denver2) Qualcomm Kryo, Falkor Samsung Exynos M1 (Mongoose), M2 (Mongoose)

ARMv8.1-A

ARMv8.1-A compatible	Cavium ThunderX2

ARMv8.2-A

Cortex-A55	Allwinner A523 Samsung Exynos 850 UNISOC SC9863/A, T603
Cortex-A75	Qualcomm Snapdragon 670, 710, 712, 845, 850 Samsung Exynos 9820, 9825 MediaTek MT6769H/T/V/Z, MT6768, MT6779V UNISOC T310, T606, T610, T615, T616, T618, T619, T620, T700, T710, T7200, T7225, T7250, T7255, T7280, T740
Cortex-A76	Allwinner A733 Google Tensor HiSilicon Kirin 810, 820, 980, 985, 990 Qualcomm Snapdragon 480(+), 675, 678, 720G, 730(G), 732G, 765(G), 768G, 855(+), 860, 7c (Gen 2), 8c, 8cx (Gen 2) Microsoft SQ1 and SQ2 MediaTek MT6781, MT6785V, MT6789, MT6833V/P, MT6853V/T, MT6873, MT6875, Dimensity 6020, 6080, 6100+, 6300(+), MT8192 Samsung Exynos 990 UNISOC T750, T760, T765, T770, T820, T8100, T8200, T9100
Cortex-A77	MediaTek Dimensity 1000(+) Qualcomm Snapdragon 690, 750G, 865(+), 870 HiSilicon Kirin 9000 Samsung Exynos 880, 980
Cortex-A78	Google Tensor G2 MediaTek MT6877, MT6878, MT6879, MT6891, MT6893, Dimensity 7020, 7025(Ultra), 7030, 7050, 7300(Energy/X), 8000, 8020, 8050, 8100, 8200, Kompanio 900T, 1200, 1380, 1300T Qualcomm Snapdragon 4 Gen 1, 4(s) Gen 2, 695, 6 Gen 1, 6(s) Gen 3, 778G(+), 780G, 782G, 888(+) Samsung Exynos 1080, 1280, 1330, 1380, 2100
Cortex-X1	Google Tensor, Tensor G2 Qualcomm Snapdragon 888(+) Samsung Exynos 2100
Neoverse N1	Ampere Altra, Altra Max AWS Graviton2
Others	Cortex-A65, Cortex-A65AE, Cortex-A76AE, Cortex-A78C, Cortex-X1C, Neoverse E1
ARMv8.2-A compatible	Apple A11 Fujitsu A64FX HiSilicon TaiShan v110 Nvidia Tegra Xavier (Carmel) Samsung Exynos M3 (Meerkat), M4 (Cheetah), M5 (Lion)

ARMv8.3-A

ARMv8.3-A compatible	Apple A12, A12X/A12Z, S4, S5 Marvell ThunderX3

ARMv8.4-A

Neoverse V1	AWS Graviton3
ARMv8.4-A compatible	Apple A13, S6, S7, S8

ARMv8.5-A

ARMv8.5-A compatible	Apple A14, M1

ARMv8.6-A

ARMv8.6-A compatible	Apple A15, A16, A17, M2, M3

ARMv8.7-A

ARMv8.7-A compatible	Qualcomm Oryon

ARMv9.0-A

Cortex-A510	Google Tensor G3 MediaTek Dimensity 7200 (Pro/Ultra), 8300 (Ultra), 9000/9000+, 9200 Qualcomm Snapdragon 7 Gen 1, 7 Gen 3, 7s/7+ Gen 2, 8(+) Gen 1, 8 Gen 2 Samsung Exynos 2200
Cortex-A710	MediaTek Dimensity 9000/9000+ Qualcomm Snapdragon 7 Gen 1, 7 Gen 3, 7s/7+ Gen 2, 8(+) Gen 1, 8 Gen 2 Samsung Exynos 2200
Cortex-A715	Google Tensor G3 MediaTek Dimensity 7200 (Pro/Ultra), 8300 (Ultra), 9200 Qualcomm Snapdragon 7 Gen 3, 8 Gen 2
Cortex-X2	MediaTek Dimensity 9000/9000+ Qualcomm Snapdragon 7s/7+ Gen 2, 8(+) Gen 1 Samsung Exynos 2200
Cortex-X3	Google Tensor G3 MediaTek Dimensity 9200/9200+ Qualcomm Snapdragon 8 Gen 2
Neoverse N2	Alibaba YiTian 710 Microsoft Azure Cobalt 100
Neoverse V2	AWS Graviton4 Google Axion Nvidia Grace

ARMv9.2-A

Cortex-A520	Google Tensor G4 Qualcomm Snapdragon 7s/7+ Gen 3, Snapdragon 8(s) Gen 3 Samsung Exynos 2400
Cortex-A720	Google Tensor G4 MediaTek Dimensity 9300(+) Qualcomm Snapdragon 7s/7+ Gen 3, Snapdragon 8(s) Gen 3 Samsung Exynos 2400
Cortex-X4	Google Tensor G4 MediaTek Dimensity 9300(+) Qualcomm Snapdragon 7+ Gen 3, Snapdragon 8(s) Gen 3 Samsung Exynos 2400
Cortex-X925	MediaTek Dimensity 9400(+)
Neoverse N3	-
Neoverse V3	-
ARMv9.2-A compatible	Apple A18 Apple M4

Embedded ARM-based chips

Embedded
microcontrollers

Cortex-M0	Cypress PSoC 4000, 4100, 4100M, 4200, 4200DS, 4200L, 4200M Infineon XMC1000 Nordic nRF51 NXP LPC1100, LPC1200 nuvoTon NuMicro Sonix SN32F700 STMicroelectronics STM32 F0 Toshiba TX00 Vorago VA108x0
Cortex-M0+	Cypress PSoC 4000S, 4100S, 4100S+, 4100PS, 4700S, FM0+ Holtek HT32F52000 Microchip (Atmel) SAM C2, D0, D1, D2, DA, L2, R2, R3 NXP LPC800, LPC11E60, LPC11U60 NXP (Freescale) Kinetis E, EA, L, M, V1, W0 Raspberry Pi RP2040 Renesas Synergy S1 Silicon Labs (Energy Micro) EFM32 Zero, Happy STMicroelectronics STM32 L0
Cortex-M1	Altera FPGAs Cyclone-II, Cyclone-III, Stratix-II, Stratix-III Microsemi (Actel) FPGAs Fusion, IGLOO/e, ProASIC3L, ProASIC3/E Xilinx FPGAs Spartan-3, Virtex-2-3-4
Cortex-M3	Actel SmartFusion, SmartFusion 2 Analog Devices ADuCM300 Cypress PSoC 5000, 5000LP, FM3 Fujitsu FM3 Holtek HT32F Microchip (Atmel) SAM 3A, 3N, 3S, 3U, 3X NXP LPC1300, LPC1700, LPC1800 ON Semiconductor Q32M210 Silicon Labs Precision32 Silicon Labs (Energy Micro) EFM32 Tiny, Gecko, Leopard, Giant STMicroelectronics STM32 F1, F2, L1 Texas Instruments F28, LM3, TMS470, OMAP 4 Toshiba TX03
Cortex-M4	Microchip (Atmel) SAM 4L, 4N, 4S NXP (Freescale) Kinetis K, W2 Renesas RA4W1, RA6M1, RA6M2, RA6M3, RA6T1
Cortex-M4F	Cypress 6200, FM4 Infineon XMC4000 Microchip (Atmel) SAM 4C, 4E, D5, E5, G5 Microchip CEC1302 Nordic nRF52 NXP LPC4000, LPC4300 NXP (Freescale) Kinetis K, V3, V4 Renesas Synergy S3, S5, S7 Silicon Labs (Energy Micro) EFM32 Wonder STMicroelectronics STM32 F3, F4, L4, L4+, WB Texas Instruments LM4F/TM4C, MSP432 Toshiba TX04
Cortex-M7F	Microchip (Atmel) SAM E7, S7, V7 NXP (Freescale) Kinetis KV5x, i.MX RT 10xx, i.MX RT 11xx, S32K3xx STMicroelectronics STM32 F7, H7
Cortex-M23	GigaDevice CD32E2xx Microchip (Atmel) SAM L10, L11, and PIC 32CM-LE 32CM-LS Nuvoton M23xx family, M2xx family, NUC1262, M2L31 Renesas S1JA, RA2A1, RA2L1, RA2E1, RA2E2
Cortex-M33F	Analog Devices ADUCM4 Dialog DA1469x GigaDevice GD32E5, GD32W5 Nordic nRF91, nRF5340, nRF54 NXP LPC5500, i.MX RT600 ON RSL15 Renesas RA4, RA6 ST STM32 H5, L5, U5, WBA Silicon Labs Wireless Gecko Series 2
Cortex-M35P	STMicroelectronics ST33K
Cortex-M55F	Alif Semiconductor Ensemble Infineon PSoC Edge
Cortex-M85F	Renesas RA8

Real-time
microprocessors

Cortex-R4F	Texas Instruments RM4, TMS570 Renesas RZ/T1
Cortex-R5F	Scaleo OLEA Texas Instruments RM57, AM2 Xilinx Versal, ZynqMP, ZynqRF
Cortex-R7F	Renesas RZ/G2E, RZ/G2H, RZ/G2M, RZ/G2N
Cortex-R52F	NXP S32Z, S32E Renesas RZ/N2L, RZ/T2L, RZ/T2M
Cortex-R52+F	STMicroelectronics Stellar G, Stellar P

Classic ARM-based chips

Classic
processors

ARM7	Atmel SAM7L, SAM7S, SAM7SE, SAM7X, SAM7XC, AT91CAP7, AT91M, AT91R Cirrus Logic PS7xxx, EP7xxx Mediatek MT62xx NXP LPC2100, LPC2200, LPC2300, LPC2400, LH7 STMicroelectronics STR7
ARM9	Aspeed AST2400 Atmel SAM9G, SAM9M, SAM9N, SAM9R, SAM9X, SAM9XE, SAM926x, AT91CAP9 Cirrus Logic EP9xxx Freescale i.MX1x, i.MX2x Nuvoton NUC900 NXP LPC2900, LPC3000, LH7A Philips Nexperia PNX4008 Rockchip RK27xx, RK28xx Samsung S3C24xx STMicroelectronics Nomadik STn881x STMicroelectronics STR9 Texas Instruments OMAP 1, AM1x, DaVinci VIA WonderMedia WM8505/8650 ZiiLABS ZMS-05
ARM11	Broadcom BCM2835 Cavium CNS3xxx Freescale i.MX3x Infotmic IMAPX210/220 Mindspeed Comcerto 1000 Nvidia Tegra APX, 6xx Qualcomm MSM7000, Snapdragon S1 Samsung S3C64xx, S5P64xx ST-NXP Wireless Nomadik STn882x Telechips TCC8902 Texas Instruments OMAP 2 VIA WonderMedia WM87x0
ARMv2a compatible	Amber (open FPGA core)
ARMv4 compatible	Faraday FA526, FA626 DEC/Intel StrongARM
ARMv5TE compatible	Intel/Marvell XScale Marvell Sheeva, Feroceon, Jolteon, Mohawk Faraday FA606TE, FA616TE, FA626TE, FA726TE

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Misplaced Pages

Processors

Designed by ARM

Designed by third parties

Timeline

See also

References

Further reading