Misplaced Pages

Instructions that have at some point been present as documented instructions in one or more x86 processors, but where the processor series containing the instructions are discontinued or superseded, with no known plans to reintroduce the instructions.

Intel instructions

i386 instructions

The following instructions were introduced in the Intel 80386, but later discontinued:

Itanium instructions

These instructions are only present in the x86 operation mode of early Intel Itanium processors with hardware support for x86. This support was added in "Merced" and removed in "Montecito", replaced with software emulation.

MPX instructions

These instructions were introduced in 6th generation Intel Core "Skylake" CPUs. The last CPU generation to support them was the 9th generation Core "Coffee Lake" CPUs.

Intel MPX adds 4 new registers, BND0 to BND3, that each contains a pair of addresses. MPX also defines a bounds-table as a 2-level directory/table data structure in memory that contains sets of upper/lower bounds.

1. For all of the MPX instructions, 16-bit addressing is disallowed − this effectively makes the address-size override prefix 67h mandatory in 16-bit mode and prohibited in 32-bit mode. In 64-bit mode, the 67h prefix is ignored for the MPX instructions − address size is always 64-bit. These behaviors are unique to the MPX instructions.
2. For BNDMK in 64-bit mode, RIP-relative addressing is not permitted and will cause #UD.
3. ^ The BNDLDX and BNDSTX instructions requires memory addressing modes that use the SIB byte − non-SIB addressing modes cause #UD.
4. ^ The BNDLDX and BNDSTX instructions produce a #BR exception if bounds directory entry is not valid (which prevents address translation).
5. The branch instructions that can accept a BND prefix are the near forms of JMP (opcodes E9 and FF /4), CALL (opcodes E8 and FF /2), RET (opcodes C2 and C3), and the short/near forms of the Jcc instructions (opcodes 70..7F and 0F 80..8F). If the BNDPRESERVE config bit is not set, then executing any of these branch instructions without the BND prefix will clear all four bounds registers. (Other branch instructions − such as e.g. far jumps, short jumps (EB), LOOP, IRET etc − do not clear the bounds registers regardless of whether an F2h prefix is present or not.)

Hardware Lock Elision

The Hardware Lock Elision feature of Intel TSX is marked in the Intel SDM as removed from 2019 onwards. This feature took the form of two instruction prefixes, XACQUIRE and XRELEASE, that could be attached to memory atomics/stores to elide the memory locking that they represent.

VP2Intersect instructions

The VP2INTERSECT instructions (an AVX-512 subset) were introduced in Tiger Lake (11th generation mobile Core processors), but were never officially supported on any other Intel processors - they are now considered deprecated and are listed in the Intel SDM as removed from 2023 onwards.

As of July 2024, the VP2INTERSECT instructions have been re-introduced on AMD Zen 5 processors.

Instructions specific to Xeon Phi processors

"Knights Corner" instructions

The first generation Xeon Phi processors, codenamed "Knights Corner" (KNC), supported a large number of instructions that are not seen in any later x86 processor. An instruction reference is available − the instructions/opcodes unique to KNC are the ones with VEX and MVEX prefixes (except for the KMOV, KNOT and KORTEST instructions − these are kept with the same opcodes and function in AVX-512, but with an added "W" appended to their instruction names).

Most of these KNC-unique instructions are similar but not identical to instructions in AVX-512 − later Xeon Phi processors replaced these instructions with AVX-512.

Early versions of AVX-512 avoided the instruction encodings used by KNC's MVEX prefix, however with the introduction of Intel APX (Advanced Performance Extensions) in 2023, some of the old KNC MVEX instruction encodings have been reused for new APX encodings. For example, both KNC and APX accept the instruction encoding 62 F1 79 48 6F 04 C1 as valid, but assign different meanings to it:

• KNC: VMOVDQA32 zmm0, k0, xmmword ptr {uint8} - vector load with data conversion
• APX: VMOVDQA32 zmm0, - vector load with one of the new APX extended-GPRs used as scaled index

"Knights Landing" and "Knights Mill" instructions

Some of the AVX-512 instructions in the Xeon Phi "Knights Landing" and later models belong to the AVX-512 subsets "AVX512ER", "AVX512_4FMAPS", "AVX512PF" and "AVX512_4VNNIW", all of which are unique to the Xeon Phi series of processors. The ER and PF subsets were introduced in "Knights Landing" − the 4FMAPS and 4VNNIW instructions were later added in "Knights Mill".

The ER and 4FMAPS instructions are floating-point arithmetic instructions that all follow a given pattern where:

• EVEX.W is used to specify floating-point format (0=FP32, 1=FP64)
• The bottom opcode bit is used to select between packed and scalar operation (0: packed, 1:scalar)
• For a given operation, all the scalar/packed variants belong to the same AVX-512 subset.
• The instructions all support result masking by opmask registers. The AVX512ER instructions also all support broadcast of memory operands.
• The only supported vector width is 512 bits.

Operation	AVX-512 subset	Basic opcode		FP32 instructions (W=0)			FP64 instructions (W=1)			RC/SAE
				Packed	Scalar		Packed	Scalar
Xeon Phi specific instructions (ER, 4FMAPS)
Reciprocal approximation with an accuracy of ${\displaystyle 2^{-28}}$	ER	EVEX.66.0F38 (CA/CB) /r		VRCP28PS z,z,z/m512	VRCP28SS x,x,x/m32		VRCP28PD z,z,z/m512	VRCP28SD x,x,x/m64		SAE
Reciprocal square root approximation with an accuracy of ${\displaystyle 2^{-28}}$	ER	EVEX.66.0F38 (CC/CD) /r		VRSQRT28PS z,z,z/m512	VRSQRT28SS x,x,x/m32		VRSQRT28PD z,z,z/m512	VRSQRT28SD x,x,x/m64		SAE
Exponential ${\displaystyle 2^{x}}$ approximation with ${\displaystyle 2^{-23}}$ relative error	ER	EVEX.66.0F38 C8 /r		VEXP2PS z,z/m512	No		VEXP2PD z,z/m512	No		SAE
Fused-multiply-add, 4 iterations	4FMAPS	EVEX.F2.0F38 (9A/9B) /r		V4FMADDPS z,z+3,m128	V4FMADDSS x,x+3,m128		No	No
Fused negate-multiply-add, 4 iterations	4FMAPS	EVEX.F2.0F38 (AA/AB) /r		V4FNMADDPS z,z+3,m128	V4FNMADDSS x,x+3,m128		No	No

1. ^ For the AVX512ER instructions, a numerically exact reference is available as C code.

The AVX512PF instructions are a set of 16 prefetch instructions. These instructions all use VSIB encoding, where a memory addressing mode using the SIB byte is required, and where the index part of the SIB byte is taken to index into the AVX512 vector register file rather than the GPR register file. The selected AVX512 vector register is then interpreted as a vector of indexes, causing the standard x86 base+index+displacement address calculation to be performed for each vector lane, causing one associated memory operation (prefetches in case of the AVX512PF instructions) to be performed for each active lane. The instruction encodings all follow a pattern where:

• EVEX.W is used to specify format of the prefetchable data (0:FP32, 1:FP64)
• The bottom bit of the opcode is used to indicate whether the AVX512 index register is considered a vector of sixteen signed 32-bit indexes (bit 0 not set) or eight signed 64-bit indexes (bit 0 set)
• The instructions all support operation masking by opmask registers.
• The only supported vector width is 512 bits.

The AVX512_4VNNIW instructions read a 128-bit data item from memory, containing 4 two-component vectors (each component being signed 16-bit). Then, for each of 4 consecutive AVX-512 registers, they will, for each 32-bit lane, interpret the lane as a two-component vector (signed 16-bit) and perform a dot-product with the corresponding two-component vector that was read from memory (the first two-component vector from memory is used for the first AVX-512 source register, and so on). These results are then accumulated into a destination vector register.

Xeon Phi processors (from Knights Landing onwards) also featured the PREFETCHWT1 m8 instruction (opcode 0F 0D /2, prefetch into L2 cache with intent to write) − these were the only Intel CPUs to officially support this instruction, but it continues to be supported on some non-Intel processors (e.g. Zhaoxin YongFeng).

AMD instructions

Am386 SMM instructions

A handful of instructions to support System Management Mode were introduced in the Am386SXLV and Am386DXLV processors. They were also present in the later Am486SXLV/DXLV and Elan SC300/310 processors.

The SMM functionality of these processors was implemented using Intel ICE microcode without a valid license, resulting in a lawsuit that AMD lost in late 1994. As a result of this loss, the ICE microcode was removed from all later AMD CPUs, and the SMM instructions removed with it.

These SMM instructions were also present on the IBM 386SLC and its derivatives (albeit with the LOADALL-like SMM return opcode 0F 07 named ICERET), as well as on the UMC U5S processor.

3DNow! instructions

The 3DNow! instruction set extension was introduced in the AMD K6-2, mainly adding support for floating-point SIMD instructions using the MMX registers (two FP32 components in a 64-bit vector register). The instructions were mainly promoted by AMD, but were supported on some non-AMD CPUs as well. The processors supporting 3DNow! were:

• AMD K6-2, K6-III, and all processors based on the K7, K8 and K10 microarchitectures. (Later AMD microarchitectures such as Bulldozer, Bobcat and Zen do not support 3DNow!)
• IDT WinChip 2 and 3
• VIA Cyrix III (both "Joshua" and "Samuel" variants), and the "Samuel" and "Ezra" revisions of VIA C3. (Later VIA CPUs, from C3 "Nehemiah" onwards, dropped 3DNow! in favor of SSE.)
• National Semiconductor Geode GX2; AMD Geode GX and LX.

PFRCP mm1,mm0
PFRCPIT1 mm0,mm1
PFRCPIT2 mm0,mm1

PFRSQRT mm1,mm0
MOVQ mm2,mm1
PFMUL mm1,mm1
PFRSQIT1 mm1,mm0
PFRCPIT2 mm1,mm2

1. The 3DNow! precision requirements can be fulfilled in several different ways, for example:
   • On AMD K6-2, the PFRCPIT1, PFRSQIT1 and PFRCPIT2 instructions would perform various parts of a Newton-Raphson iteration to improve the precision of a low-precision initial result from PFRCP/PFRSQRT.
   • On AMD Geode LX, the PFRCP and PFRSQRT instructions would instead compute their results with full 24-bit precision − this made it possible to turn the PFRCPIT1, PFRSQIT1 and PFRCPIT2 instructions into pure data movement instructions, performing the same operation as MOVQ.
2. The 3DNow! PMULHRW instruction has the same mnemonic as the Cyrix EMMI PMULHRW instruction, however its opcode and function differ (the EMMI instruction right-shifts its multiply-result by 15 bits, while the 3DNow! instruction right-shifts by 16 bits).

   Some assemblers/disassemblers, such as NASM, resolve this ambiguity by using the mnemonic PMULHRWA for the 3DNow! instruction and PMULHRWC for the EMMI instruction.

3. The FEMMS instruction differs from the standard MMX EMMS instruction in that FEMMS makes the FP/MMX register contents undefined after the instruction is executed.

3DNow! also introduced a couple of prefetch instructions: PREFETCH m8 (opcode 0F 0D /0) and PREFETCHW m8 (opcode 0F 0D /1). These instructions, unlike the rest of 3DNow!, are not discontinued but continue to be supported on modern AMD CPUs. The PREFETCHW instruction is also supported on Intel CPUs starting with 65 nm Pentium 4, albeit executed as NOP until Broadwell.

3DNow+ instructions added with Athlon and K6-2+

1. ^ The PF2IW and PI2FW instructions also existed as undocumented instructions on the original K6-2.

   The undocumented variant of PF2IW in K6-2 would set the top 16 bits of each 32-bit result lane to all-0s, while the documented variant in later processors would sign-extend the 16-bit result to 32 bits.

2. The PSWAPD instruction uses same opcode as the older undocumented K6-2 PSWAPW instruction.

3DNow! instructions specific to Geode GX and LX

SSE5 derived instructions

SSE5 was a proposed SSE extension by AMD, using a new "DREX" instruction encoding to add support for new 3-operand and 4-operand instructions to SSE. The bundle did not include the full set of Intel's SSE4 instructions, making it a competitor to SSE4 rather than a successor.

AMD chose not to implement SSE5 as originally proposed − it was instead reworked into FMA4 and XOP, which provided similar functionality but with a quite different instruction encoding − using the VEX prefix for the FMA4 instructions and the new VEX-like XOP prefix for most of the remaining instructions.

XOP instructions

Introduced with the Bulldozer processor core, removed again from Zen (microarchitecture) onward.

A revision of most of the SSE5 instruction set.

The XOP instructions mostly make use of the XOP prefix, which is a 3-byte prefix with the following layout:

where:

• Overlines indicate inverted bits.
• The R/X/B bits are argument extension bits similar to the RXB bits of the REX prefix.
• mmmmm is an opcode-map specifier. While capable of encoding values from 8 to 31 (values 0 to 7 map to ModR/M-encoded variants of the older POP instruction, making them unusable for XOP), only maps 8, 9 and 0Ah were ever used: map 8 for instructions that take an 8-bit immediate, map 9 for instructions that don't take an immediate, and map 0Ah for instructions that take a 32-bit immediate.
• W is used in a couple of different ways:
  • For XOP vector instructions, W is used to swap the last two vector source arguments to the instruction. For instructions that allow W=1, encodings with W=0 allow the second-to-last vector argument to be a memory argument, while encodings with W=1 allow the last vector argument to be a memory argument. For instructions that don't allow their last two vector arguments to be swapped, W is required to be 0.
  • For XOP-encoded integer-register instructions (the TBM and LWP instruction set extensions, see below), W is used for operand size. (0=32-bit, 1=64-bit)
• vvvv is an extra source register argument, normally the first non-r/m source argument for instructions with ≥3 register arguments.
• L is a vector length specifier. L=1 indicates 256-bit operation, L=0 indicates scalar or 128-bit operation.
• pp is an embedded prefix − nominally 0/1/2/3=none/66h/F2h/F3h, but only 0 was ever used with any of the instructions defined for the XOP prefix.

The XOP instructions encoded with the XOP prefix are as follows:

1. ^ For each VPCOM* instruction, a series of alias mnemonics are available for the instruction, one for each of the eight comparison functions encodable in the imm8 argument. These alias mnemonics specify the comparison to perform after the "VPCOM" part of the mnemonic. For example:
   • VPCOMEQB xmm1,xmm2,xmm3 is an alias for VPCOMB xmm1,xmm2,xmm3,4
   • VPCOMFALSEUQ xmm1,xmm2, is an alias for VPCOMUQ xmm1,xmm2,,6

XOP also included two vector instructions that used the VEX prefix instead of the XOP prefix:

The instructions VPERMIL2PD and VPERMIL2PS were originally defined by Intel in early drafts of the AVX specification − they were removed in later drafts and were never implemented in any Intel processor. They were, however, implemented by AMD, who designated them as being a part of the XOP instruction set extension. (Like the other parts of XOP, they've been removed in AMD Zen.)

FMA4 instructions

Supported in AMD processors starting with the Bulldozer architecture, removed in Zen. Not supported by any Intel chip as of 2023.

Fused multiply-add with four operands. FMA4 was realized in hardware before FMA3.

Trailing Bit Manipulation Instructions

AMD introduced TBM together with BMI1 in its Piledriver line of processors; later AMD Jaguar and Zen-based processors do not support TBM. No Intel processors (as of 2023) support TBM.

The TBM instructions are all encoded using the XOP prefix. They are all available in 32-bit and 64-bit forms, selected with the XOP.W bit (0=32bit, 1=64bit). (XOP.W is ignored outside 64-bit mode.) Like all instructions encoded with VEX/XOP prefixes, they are unavailable in Real Mode and Virtual-8086 mode.

1. For BEXTR, a register form is available as part of BMI1.

Lightweight Profiling instructions

The AMD Lightweight Profiling (LWP) feature was introduced in AMD Bulldozer and removed in AMD Zen. On all supported CPUs, the latest available microcode updates have disabled LWP due to Spectre mitigations.

These instructions are available in Ring 3, but not available in Real Mode and Virtual-8086 mode. All of them use the XOP prefix.

1. ^ The address used by LLWPCB and SLWPCB is an effective-address, specified relative to the DS: segment base address. LLWPCB converts this effective-address to a linear-address by adding the DS base address to it, and SLWPCB converts it back by subtracting the DS base address. Changing the DS base address while LWP is enabled will thereby cause SLWPCB to return a different address than what was specified to LLWPCB, and may also cause XSAVE to fail to save LWP state properly.

Instructions from other vendors

Instructions specific to NEC V-series processors

These instructions are specific to the NEC V20/V30 CPUs and their successors, and do not appear in any non-NEC CPUs. Many of their opcodes have been reassigned to other instructions in later non-NEC CPUs.

Instructions specific to Cyrix and Geode CPUs

These instructions are present in Cyrix CPUs as well as NatSemi/AMD Geode CPUs derived from Cyrix microarchitectures (Geode GX and LX, but not NX). They are also present in Cyrix manufacturing partner CPUs from IBM, ST and TI, as well as the VIA Cyrix III ("Joshua" core only, not "Samuel") and a few SoCs such as STPC ATLAS and ZFMicro ZFx86. Many of these opcodes have been reassigned to other instructions in later non-Cyrix CPUs.

1. The Cyrix SMM instructions also include RSM (0F AA; Return from System Management mode), however, RSM is not a Cyrix-specific instruction, and it continues to exist in modern non-Cyrix x86 processors.
2. RSDC with CS as a destination register is only supported on NatSemi Geode GX2 and AMD Geode GX/LX - on other processors, it causes #UD.
3. Some assemblers/disassemblers, such as NASM, use the instruction mnemonic SMINTOLD for the 0F 7E encoding.
4. ^ For the RDSHR and WRSHR instructions, Cyrix's documentation specifies that the instruction accepts a ModR/M byte but does not specify the encoding of the ModR/M byte's reg field. NASM v0.98.31 and later uses /0 for these instructions, while sandpile.org's opcode tables indicate that the reg field is ignored for these instructions.

Cyrix EMMI instructions

These instructions were introduced in the Cyrix 6x86MX and MII processors, and were also present in the MediaGXm and Geode GX1 processors. (In later non-Cyrix processors, all of their opcodes have been used for SSE or SSE2 instructions.)

These instructions are integer SIMD instructions acting on 64-bit vectors in MMX registers or memory. Each instruction takes two explicit operands, where the first one is an MMX register operand and the second one is either a memory operand or a second MMX register. In addition, several of the instructions take an implied operand, which is an MMX register implied from the first operand as follows:

In the instruction descriptions in the below table, arg1 and arg2 refer to the two explicit operands of the instruction, and imp to the implied operand.

1. Implementations differ on whether the PAVEB instruction treats the bytes as signed or unsigned.
2. ^ For PDISTIB, PMACHRIW and the PMV* instructions, the second explicit operand is required to be a memory operand − register operands are not supported.
3. The Cyrix EMMI PMULHRW instruction has the same mnemonic as the 3DNow! PMULHRW instruction, however its opcode and function differ (the EMMI instruction right-shifts its multiply-result by 15 bits, while the 3DNow! instruction right-shifts by 16 bits).

   Some assemblers/disassemblers, such as NASM, resolve this ambiguity by using the mnemonic PMULHRWA for the 3DNow! instruction and PMULHRWC for the EMMI instruction.

Instructions specific to VIA Technologies CPUs

All VIA C3 processors support the VIA AIS (Alternate Instruction Set). The x86 instructions present in these processors to support AIS are:

These instructions are not present in VIA C7 or any later VIA processor.

Instructions specific to Chips and Technologies CPUs

The C&T F8680 PC/Chip is a system-on-a-chip featuring an 80186-compatible CPU core, with a few additional instructions to support the F8680-specific "SuperState R" supervisor/system-management feature. Some of the added instructions for "SuperState R" are:

C&T also developed a 386-compatible processor known as the Super386. This processor supports, in addition to the basic Intel 386 instruction set, a number of instructions to support the Super386-specific "SuperState V" system-management feature. The added instructions for "SuperState V" are:

Instructions specific to ALi/Nvidia/DM&P M6117 MCUs

The M6117 series of embedded microcontrollers feature an Intel 386SX compatible CPU core derived from V.M. Technology (VMT) VM386SX+ processor. VMT VM386SX+ adds a few processor specific additions to the Intel 386 instruction set. The ones documented for DM&P M6117D are:

Instructions present in specific 80387 clones

Several 80387-class floating-point coprocessors provided extra instructions in addition to the standard 80387 ones − none of these are supported in later processors:

1. The FNSTSG AX instruction can be executed not just on the Intel 387SL FPU but on the Intel 387SX as well - executing the instruction immediately after an FNINIT will cause the instruction to return 0000h on 387SX, but a nonzero signature value on the 387SL.

See also

• x86 instruction listings

References

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53. AMD, AMD Geode GX1 Processor Data Book, rev 5.0, dec 2003, p. 226. Archived on 20 Apr 2020.
54. Cyrix, Application Note 108 − Cyrix Extensions to the Multimedia Instruction Set, rev 0.93, 9 sep 1998, page 7
55. ^ VIA Technologies, VIA C3 Samuel 2 Processor Datasheet, version 1.10, January 2002 - publicly available datasheet that lists the 0F 3F and 8D 84 00 imm32 AIS opcodes (without mnemonics) on page 60. Archived from the original on 10 Apr 2004.
56. VIA, VIA C3 Processor Alternate Instruction Set Programming Reference, version 0.25, november 2002. Accessed on Apr 26, 2023.
57. VIA, VIA C3 Processor Alternate Instruction Set Application Note, version 0.24, 2002, page 14. Accessed on Apr 26, 2023.
58. BYTE Magazine, november 1991, page 245
59. Institute Of Oceanographic Sciences, Sonic buoy − Formatter Handbook contains some F8680 instruction macros on page 34. Archived on Nov 4, 2018.
60. The F8680 PC/Chip System Design Guide contains descriptions of many of the F8680 CREG registers.
61. Michal Necasek, More on the C&T Super386
62. Corexor, Calling C&T SCALL safely, 5 Dec 2015. Archived on 27 Oct 2020.
63. DM&P, M6117D : System on a chip, pages 31,34,68. Archived on Jul 20,2006.
64. Intel "Intel287 XL/XLT Math Coprocessor", (oct 1992, order no 290376-003) p.33
65. Intel "Intel387 SL Mobile Math Coprocessor" (feb 1992, order no 290427-001), appendix A. Located on Jan 7, 2022 by searching for "intel387 sl" at datasheetarchive.com. Archived on Jan 7, 2022.
66. Desmond Yuen, Intel's SL Architecture: Designing Portable Applications, (1993, ISBN 0-07-911336-2) p.127
67. ^ IIT 3c87 Advanced Math CoProcessor Data Book
68. Harald Feldmann, Hamarsoft 86BUGS List
69. ^ Norbert Juffa "Everything You Always Wanted To Know About Math Coprocessors", 01-oct-94 revision
70. ^ Robert L. Hummel, PC Magazine Programmer's Technical Reference, 1992, ISBN 1-56276-016-5, pages 670-672 and 710.

• X86 instructions
• Instruction set listings