Misplaced Pages

Integrated circuits and certain other electronic components are put into protective packages to allow easy handling and assembly onto printed circuit boards and to protect the devices from damage. A very large number of package types exist. Some package types have standardized dimensions and tolerances, and are registered with trade industry associations such as JEDEC and Pro Electron. Other types are proprietary designations that may be made by only one or two manufacturers. Integrated circuit packaging is the last assembly process before testing and shipping devices to customers.

Occasionally specially-processed integrated circuit dies are prepared for direct connections to a substrate without an intermediate header or carrier. In flip chip systems the IC is connected by solder bumps to a substrate. In beam-lead technology, the metallized pads that would be used for wire bonding connections in a conventional chip are thickened and extended to allow external connections to the circuit. Assemblies using "bare" chips have additional packaging or filling with epoxy to protect the devices from moisture.

Through-hole packages

Through-hole technology uses holes drilled through the printed circuit board (PCB) for mounting the components. The component has leads that are soldered to pads on the PCB to electrically and mechanically connect them to the PCB.

Surface mount

Chip on board is a packaging technique that directly connects a die to a PCB, without an interposer or lead frame.

Chip carrier

A chip carrier is a rectangular package with contacts on all four edges. Leaded chip carriers have metal leads wrapped around the edge of the package, in the shape of a letter J. Leadless chip carriers have metal pads on the edges. Chip carrier packages may be made of ceramic or plastic and are usually secured to a printed circuit board by soldering, though sockets can be used for testing.

Pin grid arrays

Flat packages

Small outline packages

A small outline integrated circuit (SOIC) is a surface-mounted integrated circuit (IC) package which occupies an area about 30–50% less than an equivalent dual in-line package (DIP), with a typical thickness being 70% less. They are generally available in the same pin-outs as their counterpart DIP ICs.

Chip-scale packages

According to IPC's standard J-STD-012, Implementation of Flip Chip and Chip Scale Technology, in order to qualify as chip scale, the package must have an area no greater than 1.2 times that of the die and it must be a single-die, direct surface mountable package. Another criterion that is often applied to qualify these packages as CSPs is their ball pitch should be no more than 1 mm. Chip-scale package

Ball grid array

Ball grid array (BGA) uses the underside of the package to place pads with balls of solder in grid pattern as connections to PCB.

Transistor, diode, small-pin-count IC packages

• MELF: Metal electrode leadless face (usually for resistors and diodes)
• SOD: Small-outline diode.
• SOT: Small-outline transistor (also SOT-23, SOT-223, SOT-323).
• TO-XX: wide range of small pin count packages often used for discrete parts like transistors or diodes.
  • TO-3: Panel-mount with leads
  • TO-5: Metal can package with radial leads
  • TO-18: Metal can package with radial leads
  • TO-39
  • TO-46
  • TO-66: Similar shape to the TO-3 but smaller
  • TO-92: Plastic-encapsulated package with three leads
  • TO-99: Metal can package with eight radial leads
  • TO-100: Metal can package with ten radial leads, similar to TO-99
  • TO-126: Plastic-encapsulated package with three leads and a hole for mounting on a heat sink
  • TO-220: Through-hole plastic package with a (usually) metal heat sink tab and three leads
  • TO-226
  • TO-247: Plastic-encapsulated package with three leads and a hole for mounting on a heat sink
  • TO-251: Also called IPAK: SMT package similar to the DPAK but with longer leads for SMT or TH mounting
  • TO-252: (also called SOT428, DPAK): SMT package similar to the DPAK but smaller
  • TO-262: Also called I2PAK: SMT package similar to the D2PAK but with longer leads for SMT or TH mounting
  • TO-263: Also called D2PAK: SMT package similar to the TO-220 without the extended tab and mounting hole
  • TO-274: Also called Super-247: SMT package similar to the TO-247 without the mounting hole

Dimension reference

Surface-mount

C

Clearance between IC body and PCB

H

Total height

T

Lead thickness

L

Total carrier length

L_W

Lead width

L_L

Lead length

P

Pitch

Through-hole

C

Clearance between IC body and board

H

Total height

T

Lead thickness

L

Total carrier length

L_W

Lead width

L_L

Lead length

P

Pitch

W_B

IC body width

W_L

Lead-to-lead width

Package dimensions

All measurements below are given in mm. To convert mm to mils, divide mm by 0.0254 (i.e., 2.54 mm / 0.0254 = 100 mil).

C

Clearance between package body and PCB.

H

Height of package from pin tip to top of package.

T

Thickness of pin.

L

Length of package body only.

L_W

Pin width.

L_L

Pin length from package to pin tip.

P

Pin pitch (distance between conductors to the PCB).

W_B

Width of the package body only.

W_L

Length from pin tip to pin tip on the opposite side.

Dual row

Image	Family	Pin	Name	Package	L	WB	WL	H	C	P	LL	T	LW
	DIP	Y	Dual inline package	8-DIP	9.2–9.8	6.2–6.48	7.62	7.7		2.54 (0.1 in)	3.05–3.6		1.14–1.73
				32-DIP			15.24			2.54 (0.1 in)
	LFCSP	N	Lead-frame chip-scale package							0.5
	MSOP	Y	Mini small-outline package	8-MSOP	3	3	4.9	1.1	0.10	0.65	0.95	0.18	0.17–0.27
				10-MSOP	3	3	4.9	1.1	0.10	0.5	0.95	0.18	0.17–0.27
				16-MSOP	4.04	3	4.9	1.1	0.10	0.5	0.95	0.18	0.17–0.27
	SO SOIC SOP	Y	Small-outline integrated circuit	8-SOIC	4.8–5.0	3.9	5.8–6.2	1.72	0.10–0.25	1.27	1.05	0.19–0.25	0.39–0.46
				14-SOIC	8.55–8.75	3.9	5.8–6.2	1.72	0.10–0.25	1.27	1.05	0.19–0.25	0.39–0.46
				16-SOIC	9.9–10	3.9	5.8–6.2	1.72	0.10–0.25	1.27	1.05	0.19–0.25	0.39–0.46
				16-SOIC	10.1–10.5	7.5	10.00–10.65	2.65	0.10–0.30	1.27	1.4	0.23–0.32	0.38–0.40
	SOT	Y	Small-outline transistor	SOT-23-6	2.9	1.6	2.8	1.45		0.95	0.6		0.22–0.38
	SSOP	Y	Shrink small-outline package							0.65
	TDFN	N	Thin dual flat no-lead	8-TDFN	3	3	3	0.7–0.8		0.65	—		0.19–0.3
	TSOP	Y	Thin small-outline package							0.5
	TSSOP	Y	Thin shrink small-outline package	8-TSSOP	2.9-3.1	4.3-4.5	6.4	1.2	0.15	0.65		0.09–0.2	0.19–0.3
		Y		14-TSSOP	4.9-5.1	4.3-4.5	6.4	1.1	0.05-0.15	0.65		0.09-0.2	0.19-0.30
				20-TSSOP	6.4-6.6	4.3-4.5	6.4	1.1	.05-0.15	0.65		0.09-0.2	0.19-0.30
	μSOP	Y	Micro small-outline package	μSOP-8	3		4.9	1.1		0.65
	US8	Y	US8 package		2	2.3	3.1	.7		0.5

Quad rows

Image	Family	Pin	Name	Package	WB	WL	H	C	L	P	LL	T	LW
	PLCC	N	Plastic leaded chip-carrier							1.27
	CLCC	N	Ceramic leadless chip-carrier	48-CLCC	14.22	14.22	2.21		14.22	1.016	—		0.508
	LQFP	Y	Low-profile quad flat package							0.50
	TQFP	Y	Thin quad flat-package	TQFP-44	10.00	12.00		0.35–0.50		0.80	1.00	0.09–0.20	0.30–0.45
	TQFN	N	Thin quad flat no-lead

LGA

Multi-chip packages

A variety of techniques for interconnecting several chips within a single package have been proposed and researched:

• SiP (system in package)
• PoP (package on package)
• 3D-SICs, Monolithic 3D ICs, and other three-dimensional integrated circuits
• Multi-chip module
• WSI (wafer-scale integration)
• Proximity communication

By terminal count

Surface-mount components are usually smaller than their counterparts with leads, and are designed to be handled by machines rather than by humans. The electronics industry has standardized package shapes and sizes (the leading standardisation body is JEDEC).

The codes given in the chart below usually tell the length and width of the components in tenths of millimeters or hundredths of inches. For example, a metric 2520 component is 2.5 mm by 2.0 mm which corresponds roughly to 0.10 inches by 0.08 inches (hence, imperial size is 1008). Exceptions occur for imperial in the two smallest rectangular passive sizes. The metric codes still represent the dimensions in mm, even though the imperial size codes are no longer aligned. Problematically, some manufacturers are developing metric 0201 components with dimensions of 0.25 mm × 0.125 mm (0.0098 in × 0.0049 in), but the imperial 01005 name is already being used for the 0.4 mm × 0.2 mm (0.0157 in × 0.0079 in) package. These increasingly small sizes, especially 0201 and 01005, can sometimes be a challenge from a manufacturability or reliability perspective.

Two-terminal packages

Rectangular passive components

Mostly resistors and capacitors.

Tantalum capacitors

Aluminum capacitors

Small-outline diode (SOD)

Metal electrode leadless face (MELF)

Mostly resistors and diodes; barrel shaped components, dimensions do not match those of rectangular references for identical codes.

DO-214

Commonly used for rectifier, Schottky, and other diodes.

Three- and four-terminal packages

Small-outline transistor (SOT)

Other

• DPAK (TO-252, SOT-428): Discrete Packaging. Developed by Motorola to house higher powered devices. Comes in three or five-terminal versions.
• D2PAK (TO-263, SOT-404): Bigger than the DPAK; basically a surface mount equivalent of the TO220 through-hole package. Comes in 3, 5, 6, 7, 8 or 9-terminal versions.
• D3PAK (TO-268): Even larger than D2PAK.

Five- and six-terminal packages

Small-outline transistor (SOT)

Packages with more than six terminals

Dual-in-line

• Flatpack was one of the earliest surface-mounted packages.
• Small-outline integrated circuit (SOIC): dual-in-line, 8 or more pins, gull-wing lead form, pin spacing 1.27 mm.
• Small-outline package, J-leaded (SOJ): The same as SOIC except J-leaded.
• Thin small-outline package (TSOP): thinner than SOIC with smaller pin spacing of 0.5 mm.
• Shrink small-outline package (SSOP): pin spacing of 0.65 mm, sometimes 0.635 mm or in some cases 0.8 mm.
• Thin shrink small-outline package (TSSOP).
• Quarter-size small-outline package (QSOP): with pin spacing of 0.635 mm.
• Very small outline package (VSOP): even smaller than QSOP; 0.4-, 0.5-, or 0.65-mm pin spacing.
• Dual flat no-lead (DFN): smaller footprint than leaded equivalent.

Quad-in-line

• Plastic leaded chip carrier (PLCC): square, J-lead, pin spacing 1.27 mm
• Quad flat package (QFP): various sizes, with pins on all four sides
• Low-profile quad flat-package (LQFP): 1.4 mm high, varying sized and pins on all four sides
• Plastic quad flat-pack (PQFP), a square with pins on all four sides, 44 or more pins
• Ceramic quad flat-pack (CQFP): similar to PQFP
• Metric quad flat-pack (MQFP): a QFP package with metric pin distribution
• Thin quad flat-pack (TQFP), a thinner version of LQFP
• Quad flat no-lead (QFN): smaller footprint than leaded equivalent
• Leadless chip carrier (LCC): contacts are recessed vertically to "wick-in" solder. Common in aviation electronics because of robustness to mechanical vibration.
• Micro leadframe package (MLP, MLF): with a 0.5 mm contact pitch, no leads (same as QFN)
• Power quad flat no-lead (PQFN): with exposed die-pads for heatsinking

Grid arrays

• Ball grid array (BGA): A square or rectangular array of solder balls on one surface, ball spacing typically 1.27 mm (0.050 in)
  • Fine-pitch ball grid array (FBGA): A square or rectangular array of solder balls on one surface
  • Low-profile fine-pitch ball grid array (LFBGA): A square or rectangular array of solder balls on one surface, ball spacing typically 0.8 mm
  • Micro ball grid array (μBGA): Ball spacing less than 1 mm
  • Thin fine-pitch ball grid array (TFBGA): A square or rectangular array of solder balls on one surface, ball spacing typically 0.5 mm
• Land grid array (LGA): An array of bare lands only. Similar to in appearance to QFN, but mating is by spring pins within a socket rather than solder.
• Column grid array (CGA): A circuit package in which the input and output points are high-temperature solder cylinders or columns arranged in a grid pattern.
  • Ceramic column grid array (CCGA): A circuit package in which the input and output points are high-temperature solder cylinders or columns arranged in a grid pattern. The body of the component is ceramic.
• Lead-less package (LLP): A package with metric pin distribution (0.5 mm pitch).

Non-packaged devices

Although surface-mount, these devices require specific process for assembly.

• Chip-on-board (COB), a bare silicon chip, that is usually an integrated circuit, is supplied without a package (which is usually a lead frame overmolded with epoxy) and is attached, often with epoxy, directly to a circuit board. The chip is then wire bonded and protected from mechanical damage and contamination by an epoxy "glob-top".
• Chip-on-flex (COF), a variation of COB, where a chip is mounted directly to a flex circuit. Tape-automated bonding process is also a chip-on-flex process as well.
• Chip-on-glass (COG), a variation of COB, where a chip, typically a liquid crystal display (LCD) controller, is mounted directly on glass.
• Chip-on-wire (COW), a variation of COB, where a chip, typically a LED or RFID chip, is mounted directly on wire, thus making it a very thin and flexible wire. Such wire may then be covered with cotton, glass or other materials to make into smart textiles or electronic textiles.

There are often subtle variations in package details from manufacturer to manufacturer, and even though standard designations are used, designers need to confirm dimensions when laying out printed circuit boards.

See also

• Surface-mount technology
• Three-dimensional integrated circuit
• Interposer
• IPC (electronics)
• List of chip carriers
• List of electronics package dimensions
• Redistribution layer
• Small-outline transistor
• Wafer-level packaging

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External links

• JEDEC JEP95 official list of all (over 500) standard electronic packages
• Fairchild Index of Package Information
• An illustrated listing of different package types, with links to typical dimensions/features of each
• Intersil packaging information
• ICpackage.org
• Solder Pad Layout Dimensions
• International Microelectronics And Packaging Society

• Chip carriers
• Semiconductor packages
• Electronics lists