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Montecito is the code-name of a major release of Intel's Itanium 2Processor Family (IPF), which implements the Intel Itanium architecture on a dual-core processor. It was officially launched by Intel on July 18, 2006, as the "Dual-Core Intel Itanium 2 processor". According to Intel, Montecito doubles performance versus the previous, single-core Itanium 2 processor, and reduces power consumption by about 20%. It also adds multi-threading capabilities (two threads per core), a greatly expanded cache subsystem (12 MB per core), and silicon support for virtualization.
2-way coarse-grained multithreading per core (not simultaneous). Montecito-flavour of multi-threading is dubbed temporal, or TMT. This is also known as switch-on-event multithreading, or SoEMT. The two separate threads do not run simultaneously, but the core switches thread in case of a high latency event, like an L3 cache miss which would otherwise stall execution. By this technique, multi-threaded workloads, including database-like workloads, should improve by 15-35%.
a total of 4 threads per die
separate 16 KB Instruction L1 and 16 KB Data L1 cache per core
separate 1 MB Instruction L2 and 256 KB Data L2 cache per core, improved hierarchy
12 MB L3 cache per core, 24 MB L3 per die
1.72 billion transistors per die, which is added up from:
Lower power consumption and thermal dissipation than earlier flagship Itaniums, despite the high transistor count; 75-104 W. This is mainly achieved by applying different types of transistors. By default, slower and low-leakage transistors were used, while high-speed, thus high-leakage ones where it was necessary.
Advanced compensation for errors in cache, for reliable operation under mission-critical workloads. This was code-named Pellston technology during development, and has recently been renamed Intel Cache Safe Technology.
Virtualization technology allowing multiple OS instances per chip. This was known as Silvervale technology during development, and is now called Intel Virtualization Technology.
Improved, higher bandwidthfront side bus (FSB), with three times the capacity of the existing bus design. It is meant to be at system level (per node, with 4 dies). System throughput per node should be at least 21 GB/s, which suggest dual 333.333 MHz (double pumped, resulting 2×667 effective MHz) front side bus. However, it is up to system integrators how they organize their bus topology.
All Montecito processors support 533 MHz / 400 MHz FSB speed.
Also available with legacy FSB for upgrading existing system designs.
Eliminates the hardware-based x86 instruction emulation circuitry, in favor of the more efficient software-based IA-32 Execution Layer.
On October 25, 2005, Intel announced that the first dual-core Itanium processor would be delayed until "the middle of next year." Archived 2008-05-16 at the Wayback Machine Montecito was launched on July 18, 2006. Due to unspecified issues, Intel's Foxton power management technology was disabled in the first release of Montecito, and the front-side bus frequency was reduced to 267 MHz (533.333 MHz effective) instead of the 333 MHz speed originally scheduled for the design .
At the time of launch, the following models and pricing were available:
