| General information | |
|---|---|
| Designed by | Indian Institute of Technology, Madras |
| Common manufacturers | |
| Architecture and classification | |
| Application | SoC, development boards, based software platform, IOT |
| Instruction set | RISC-V |
| Models |
|
Shakti (stylized as SHAKTI) is an open-source initiative by the Reconfigurable Intelligent Systems Engineering (RISE) group at Indian Institute of Technology, Madras (IIT Madras) to develop the first indigenous Indian industrial-grade processor. The aims of the Shakti initiative include building an open source production-grade processor, complete systems on a chip (SoCs), microprocessor development boards, and a Shakti-based software platform. The main focus of the team is computer architecture research to develop SoCs, which are competitive with commercial offerings in the market in area, power, and performance. All the source codes for Shakti are open-sourced under the Modified BSD License. The project was funded by the Ministry of Electronics and Information Technology (MeITY), Government of India.
Processors
Shakti processors are based on the RISC-V instruction set architecture (ISA). The processors are designed to have either 22 nm process fin field-effect transistor (FinFET) or 180 nm process complementary metal–oxide–semiconductor (CMOS) technology nodes depending on the manufacturing semiconductor fabrication plant (foundry).
Shakti plans a family of processors as part of its road-map, catering to different segments of the market. They have been broadly categorized into "Base Processors", "Multi-Core Processors" and "Experimental Processors".
The E and C-classes core are for Internet of things (IoT), embedded system, and desktop computer markets. The processor design is free of any royalty and is open-source licensed under the modified BSD License.
E-class and C-class cores are both implemented in Bluespec SystemVerilog (BSV) language, a Haskell dialect.
The Shakti project aims to build 6 variants of processors based on the RISC-V ISA.
Base classes of processors
E-class
The E-class are 32- and 64-bit microcontrollers able to support all extensions of the RISC-V ISA, for low-power and low computer applications. The E-class is an in-order 3 stage pipeline having an operational frequency of less than 200 MHz on silicon. It is positioned against ARM's M-class (Cortex-M series) cores. It can run real-time operating systems like FreeRTOS, Zephyr, and eChronos. Market segments of E-class processor support smart cards, IoT devices, motor controls, and robotic platforms.
E-arty35T is a SoC built around E-class. The E-arty35T SoC is a single-chip 32-bit E-class microcontroller with 128kB RAM. It has 32 general-purpose input/output (GPIO) pins (out of which upper 16 GPIO pins are dedicated to onboard LEDs and switches), a platform level interrupt controller (PLIC), a Counter, 2 Serial Peripheral Interface (SPI), 2 universal asynchronous receiver-transmitter (UART), 1 Inter-Integrated Circuit (I²C), 6 pulse-width modulator (PWM) and an inbuilt Xilinx analog-to-digital converter (X-ADC).
C-class
The C-class is a 64-bit controller class of processor, for mid-range embedded application. The core is highly optimized, 6-stage in-order design with MMU support and the capability to run operating systems like Linux and Sel4. It is extremely configurable with the support of the standard RV64GC ISA extensions. It is for mid-range compute systems running over 200-800 MHz. It can also be customized up to 2 GHz. It is positioned against ARM's Cortex A35/A55. The application domain of this class ranges from embedded systems, motor-control, IoT, storage, industrial applications to low-cost high-performance Linux based applications such as networking, gateways etc.
C-arty100T is a SoC built around the C-class. The C-arty100T SoC is a single-chip 64-bit C-class microcontroller with 128MB DDR3 RAM, 16 General Purpose Input Output (GPIO) pins, a Platform Level Interrupt Controller (PLIC), a Counter, 1 Universal Asynchronous Receiver Transmitter (UART) and 1 Inter-Integrated Circuit (I²C). It is for mid-range application workloads with a very low power use and support for optional memory protection.
I-class
The I-class is a 64-bit processor for the compute, mobile, storage, and networking platforms. Its features include out-of-order execution, multithreading, aggressive branch prediction, non-blocking caches and deep instruction pipelining stages. The operational clock frequency of this processor is 1.5-2.5 GHz. As of April 2020, the team was working on implementing atomics, memory dependence prediction, instruction window/scheduler optimizations, implementation of some functional units, performance analysis/projections, optimizations to meet first-cut target frequency on 1 GHz on 22 nm processor.
Multicore processors
M-class
A mobile class processor with a maximum of eight cores, the cores being a combination of C and I class cores. The M-class processors are for general-purpose compute, low-end server and mobile applications. The operation frequency ranges up to 2.5 GHz. It supports large issue size, quad-threaded and optional NoC fabric. The M-class processors are optimized for various power and performance goals.
S-class
The S-Class is a 64-bit superscalar, multi-threaded variant for desktop and enterprise server uses. Its supports 2–16 cores with a clock frequency of about 1.2–3 GHz.
H-class
The H-class is a 64-bit processor for highly parallel enterprise, HPC, and analytics applications. The cores can be a combination of C or I class, single-thread performance driving the core choice. The H-class has up to 128 cores with multiple accelerators per core.
Experimental processors
These are experimental/research projects which focus on developing a high security and fault tolerant processor.
T-class
The T-class is aimed to provide additional hardware support for securing information from memory-based attacks. Its design focuses on a unified hardware framework for mitigating spatial and temporal memory attacks.
F-class
The F-class is a fault-tolerant version of the base class processor. Features include redundant compute blocks (like DMR and TMR), temporal redundancy modules to detect permanent faults, lock-step core configurations, fault localization circuits, ECC for critical memory blocks and redundant bus fabrics.
Tapeouts
Two C-class processors (codenamed RIMO and Risecreek) and one E-class processor (Moushik) have been taped-out so far.
RIMO
RIMO is the code name of the Shakti C-class based SoC that has been taped-out at Semi-Conductor Laboratory (SCL) at Mohali using 180 nm process technology. The 144 sq.mm. chip has been tested to operate at a frequency of up to 70 MHz. The chip has been packaged on a 208-pin Ceramic Quad Flat Pack (CQFP).
Risecreek
CREEK is the code name of the Shakti C-class based SoC that has been taped-out at Intel's Oregon fab using a 22nm FinFET process. The 16mm² chip has been tested to operate at a frequency of up to 350 MHz. The chip has been packaged on a 208-pin Ball Grid Array (BGA).
Moushik
Moushik is the code name of the Shakti E-class based SoC that has been taped-out at SCL using 180 nm process technology. It operates in frequency of 100 MHz and developed along with a motherboard called Ardonyx 1.0.
Features of RIMO and Risecreek
Some of the features of RIMO and Risecreek are as follows:
- In-order 5 stage 64-bit microcontroller supporting the entire stable RISC-V ISA(RV64IMAFD).
- Compatible with privilege spec (v1.10) of RISC-V ISA and supports the sv39 virtualisation scheme.
- Includes a branch predictor with a Return-Address-Stack.
- Pipelined IEEE-754 compliant single and double-precision floating point units and Multi-channel direct memory access (DMA) support.
- Peripherals like 2 x I²C, 2 x UART, 2 x QSPI, a debugger, a 256KB tightly coupled memory, 32-bit GPIOs and an expansion bus that can be connected to a field-programmable gate array (FPGA).
Development boards
There are development boards for both E and C-class of processors. The details on the board support for different classes of processors are given below.
E-arty35T
- E-arty35Tis a SoC based on Shakti E class .
- E-arty35Tis supported on Artix 7 35T board.
- It has an abridged version of 32-bit E class. It includes I, M, A and C.
C-arty100T
- C-arty100Tis a SoC based on Shakti C-class.
- C-arty100Tis supported on Artix 7 100T board.
- It has an abridged version of 64-bit C-class. It includes I, M, A, F, D and C.
Commercial support
Altair Engineering from July 2021, included E-Class processor in its embedded system firmware support portfolio for its global customers.
Swadeshi Microprocessor Challenge
On December 7, 2021, the Ministry of Electronics and Information Technology honored the Swadeshi Microprocessor Challenge winners. At different phases of the challenge, participants get up to ₹4.40 crore in funding for the development of a hardware prototype and the incubation of a start-up by participating teams. C-DAC and IIT Madras made accessible for the challenge their SoCs, THEJAS32 and THEJAS64, based on VEGA 32-bit and 64-bit processors and Shakti. The participating teams successfully implemented the SoCs in a variety of designs. Ten teams became victorious from the 30 finalist teams. Team VEGA FCS FT (AI drone), received a ₹35 lakh cheque for their drone application; second-place winners, Team HWDL, received ₹30 lakh for FM Radio Data System Utilities; and third-place winners, Cytox, received ₹25 lakh for their cell count project. Each of the other teams received a check for ₹20 lakh for sharing fourth place. The teams are Astrek Innovations (lower limb exosuit for disabled), Team 6E Resources (remote monitoring and optimization of sewage treatment plant), Team Anshashodhak (unique calibration system for nuclear spectroscopy applications), Team Quicproc (wireless maternal monitoring system), Team Avrio Energy (AI Energy Meter with intelligence at edge and deep learning), and Team JayHawks (anti-theft geofencing based locking system).
Thirty finalist teams of the Swadeshi Microprocessor Challenge have been awarded incubation support by Maker Village, the largest electronic system design and production center in India.
References
- "Shakti". IIT Madras. 2021. Retrieved 2024-09-04.
- ^ Veezhinathan, Kamakoti (November 2022). "Building the Shakti Microprocessor". cacm.acm.org. Retrieved 2022-11-15.
- "IIT-Madras Develops 'India's First Microprocessor', Shakti". NDTV Gadgets 360. 2 November 2018. Retrieved 2020-04-10.
- Gala, Neel; Menon, Arjun; Bodduna, Rahul; Madhusudan, G. S.; Kamakoti, V. (January 2016). Shakti Processors: An Open-Source Hardware Initiative. 2016 29th International Conference on VLSI Design and 2016 15th International Conference on Embedded Systems (VLSID). pp. 7–8. doi:10.1109/VLSID.2016.130. ISBN 978-1-4673-8700-2. S2CID 14815714.
- ^ "Shakti Development Board User Manual" (PDF). Shakti. Retrieved 10 April 2010.
- ^ "Shakti - The Open Source Indian Microprocessor & Microcontroller". Engineer's Asylum. 2020-04-07. Retrieved 2020-04-10.
- ^ "E-Class on ARTY-A7-35t Board". GitLab. Retrieved 2020-04-10.
- ^ "C-Class on ARTY-A7-100t Board". GitLab. Retrieved 2020-04-10.
- ^ "Processors". Shakti. Retrieved 10 April 2020.
- Ranganathan, Nitya. "Shakti I Class: Introduction" (PDF). Shakti. Retrieved 10 April 2020.
- "Shakti-T: A RISC-V Processor with Light Weight Security Extensions". Proceedings of the Hardware and Architectural Support for Security and Privacy. 25 June 2017. pp. 1–8. doi:10.1145/3092627.3092629. ISBN 9781450352666. S2CID 207646970. Retrieved 2020-04-10.
- Gupta, Sukrat; Gala, Neel; Madhusudan, G. S.; Kamakoti, V. (November 2015). Shakti-F: A Fault Tolerant Microprocessor Architecture. 2015 IEEE 24th Asian Test Symposium (ATS). pp. 163–168. doi:10.1109/ATS.2015.35. ISBN 978-1-4673-9739-1. S2CID 7705965.
- "Meet India's Atmanirbhar Microprocessor chip 'Moushik', meant for IoT devices". WION. 24 September 2020. Retrieved 2020-09-25.
- MP, Sidharth (6 July 2021). "India's home-grown microprocessor Shakti is now part of tech-giant Altair's offerings". WION. Retrieved 2021-07-09.
- "MeitY felicitates winners of microprocessor challenge; participants get financial support". Business Today. 2021-12-07. Retrieved 2024-09-05.
- Rao, S Krishnakumar (3 December 2021). "VEGA Processors : Making India AtmaNirbhar in Swadeshi Compute Designs" (PDF). Centre for Development of Advanced Computing. Retrieved 4 September 2024.
- "Maker Village of Digital University Kera to incubate 10 winners of Swadeshi Microprocessor Challenge". English.Mathrubhumi. 2021-12-10. Retrieved 2024-09-05.