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SPICE OPUS is a free general purpose electronic circuit simulator, developed and maintained by members of EDA Group, University of Ljubljana, Slovenia. It is based on original Berkeley’s SPICE analog circuit simulator and includes various improvements and advances, such as memory-leak bug fixes and plotting tool improvements. SPICE OPUS is specially designed for fast optimization loops via its built-in optimizer.

SPICE OPUS analyses and processing is done using NUTMEG interpreted programming language, which allows interactive SPICE OPUS sessions. SPICE OPUS can also be used as a batch simulator that stores its results in output files (ASCII and binary RAW file format is supported).

History

SPICE OPUS started in the mid-1990s as a teaching and research tool for circuit design and optimization at the Faculty of Electrical Engineering, University of Ljubljana. At the time only Windows operating system was supported as this was the preferred choice of most students at that time. In 1999 a Linux version (1.0) was released with the help of the cross platform Qt library. XSPICE extensions were added in version 2.0. Several bugs were reported to be removed and features were added over the next decade. The latest addition (version 3.0) is the support of OpenVAF-compiled Verilog-A models via its OSDI interface.

Between years 2000 and 2023, SpiceOpus is reported to be used as a tool for teaching the theory of circuit simulation and algorithms in higher education in several universities.

Similarly, it has been widely used in academia for scientific research of systems, electronics and algorithms for EDA.

Overview

Available analyses

• Operating point (OP) Analysis
• Operating point Sweep Analysis (DC Analysis)
• DC Transfer Function Analysis (TF Analysis)
• Small Signal Analysis (AC Analysis)
• Pole-Zero (PZ) Analysis
• Noise (NOISE) Analysis
• Transient (TRAN) Analysis

Models

SPICE OPUS comes with several device models

• basic circuit components like votage and current sources, resistors, capacitors, bipolar transistors, diodes, ...
• advanced models like BSIM3, BSIM3SOI, BSIM4, SOI3, UFS, UFET, EKV, ...
• XSPICE code models for behavioral modeling and event-driven simulation
• special code models for small-signal modelling in frequency domain: ZARC and constant phase element (CPE).
• a library of compact models written in Verliog-A (BSIMBULK, BSIMCMG, HICUM, EKV, HiSIM, MEXTRAM, ...)

Following approaches for adding user-defined models are supported:

• Behavioral voltage and current sources (B devices)
• XSPICE code models written in C
• Verilog-A models that can be compiled with OpenVAF compiler

SPICE OPUS supports parameterized netlists, parameterized subcircuits, and topology changes without simulator restart (netclass).

As a supported simulator in PyOPUS optimization library SPICE OPUS can be used as a simulation engine for advanced circuit analyses (Monte Carlo, sensitivity, worst-case, worst-case distance) and automated design procedures (nominal design, corner-based design, yield targeting).

Schematic entry is available via an interface to the KiCAD schematic editor in the PyOPUS library or Qucs-S: Qucs circuit simulation software package. Usage of SpiceOpus is also reported in web-application for circuit schematics editing GEEC

References

1. http://www.spiceopus.si
2. PUHAN, Janez, TUMA, Tadej. Optimisation of analog circuits with SPICE 3F4. V: Proceedings of the 1997 European Conference on Circuit Theory and Design, ECCTD '97, Technical University of Budapest, Hungary, 30th August - 3rd September 1997. Budapest: Technical University of Budapest, 1997. Str. 2/177-180, ilustr.
3. PUHAN, Janez, TUMA, Tadej, FAJFAR, Iztok. SPICE for Windows 95/98/NT. Elektrotehniški vestnik. . 1998, let. 65, št. 5, str. 267-271, graf. prikazi. ISSN 0013-5852.
4. Code-level modeling in XSPICE, F. L. Cox e.a., Proceedings IEEE International Symposium on Circuits and Systems, 1992 (ISCAS 92), vol. 2, pp. 871-874, 10–13 May 1992
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6. J. Pallarès, K. Sabine, L. Terés, and F. Serra-Graells, ‘An academic EDA suite for the full-custom design of mixed-mode integrated circuits’, in 2017 IEEE International Symposium on Circuits and Systems (ISCAS), May 2017, pp. 1–4. doi: 10.1109/ISCAS.2017.8050519.
7. Chika, Ifeyinwa E., Djamel Azzi, and Roy Williams. "Students’ laboratory work performance assessment." International Conference on Interactive Computer Aided Learning (ICL2008). 2008.
8. Murthy, RS Ananda. "A Simplified Introduction to Circuit Simulation using SPICE OPUS." (2007).
9. O. Marrufo and A. O. Rodriguez, ‘Study of optimal separation of two circular phased-array coils via an equivalent circuit’, in 2005 IEEE Engineering in Medicine and Biology 27th Annual Conference, Jan. 2005, pp. 4282–4285. doi: 10.1109/IEMBS.2005.1615411.
10. Kunaver, Matevž, et al. "Synthesizing electrically equivalent circuits for use in electrochemical impedance spectroscopy through grammatical evolution." Processes 9.11 (2021): 1859.
11. S. Jemmali, A. Nehme, and J.-J. Charlot, ‘Behavioral modeling of multitechnological systems with VHDL-AMS and simulating with spice’, in Proceedings of the 2003 IEEE International Workshop on Behavioral Modeling and Simulation, Oct. 2003, pp. 92–96. doi: 10.1109/BMAS.2003.1249864.
12. S. Jemmali, J.-J. Charlot, and A. Rabhi, ‘Consumption of a SDRAM memory cell module by using Vamspicedesigner, a design tool based on VHDL-AMS and SPICE’, in IEEE International Conference on Industrial Technology, 2003, Dec. 2003, pp. 754-760 Vol.2. doi: 10.1109/ICIT.2003.1290751.
13. L. C. Chirwa, J. F. Dawson, K. F. Kam, M. P. Robinson, and N. L. Whyman, ‘Intermediate level circuit model for time-domain analysis of shielding using SPICE’, in 2003 IEEE Symposium on Electromagnetic Compatibility. Symposium Record (Cat. No.03CH37446), Aug. 2003, pp. 193–196 vol.1. doi: 10.1109/ISEMC.2003.1236590.
14. Frei, S., and R. Jobava. "Coupling of inhomogeneous fields into an automotive cable harness with arbitrary terminations." Proc. of EMC Zurich. Vol. 1. 2001.
15. Franco Peláez, Francisco Javier, et al. "SPICE Simulations of single event transients in bipolar analog integrated circuits using public information and free open source tools." (2015).
16. Olenšek, Jernej, et al. "DESA: a new hybrid global optimization method and its application to analog integrated circuit sizing." Journal of Global Optimization 44 (2009): 53-77.
17. F. Serra-Graells, A. Uranga, and N. Barniol, ‘Analog Integrated Circuit Optimization Using Spice’, in Microelectronics Education, A. M. Ionescu, M. Declercq, M. Kayal, and Y. Leblebici, Eds., Dordrecht: Springer Netherlands, 2004, pp. 169–174. doi: 10.1007/978-1-4020-2651-5_29.
18. Bürmen, Arpad, et al. "Model parameter identification with SPICE OPUS: A comparison of direct search and elitistic genetic algorithm." Proceedings of the 15th European Conference on Circuit Theory and Design, ECCTD. Vol. 1. 2001.
19. Kunaver, Matevž. "Grammatical evolution-based analog circuit synthesis." Informacije MIDEM 49.4 (2019): 229-240.
20. Starzak, L., Andrzej Napieralski, and J-J. Charlot. "VHDL-AMS: a competitor for SPICE in modeling of semiconductor devices." Modern Problems of Radio Engineering, Telecommunications and Computer Science (IEEE Cat. No. 02EX542). IEEE, 2002.
21. Tadej Tuma and Árpád Bürmen, Circuit Simulation with SPICE OPUS. Boston, MA: Birkhäuser, 2009. doi: 10.1007/978-0-8176-4867-1.
22. A. Bürmen, ‘8.1. pyopus.netlister.kicad — KiCad netlister — PyOPUS 0.10 documentation’. https://fides.fe.uni-lj.si/pyopus/download/0.10/docsrc/_build/html/netlister.kicad.html (accessed 10 May 2023).
23. https://ra3xdh.github.io/
24. F. Paulů and J. Hospodka, ‘GEEC: Graphic editor of electrical circuits’, in 2017 International Conference on Applied Electronics (AE), Sep. 2017, pp. 1–4. doi: 10.23919/AE.2017.8053604.

• Electronic circuit simulators
• Simulation software