Stub Series Terminated Logic (SSTL) is a group of electrical standards for driving transmission lines commonly used with DRAM based DDR memory IC's and memory modules. SSTL is primarily designed for driving the DDR (double-data-rate) SDRAM modules used in computer memory; however, it is also used in other applications, notably some PCI Express PHYs and other high-speed devices.
Four voltage levels for SSTL are defined:
- SSTL_3, 3.3 V, defined in EIA/JESD8-8 1996
- SSTL_2, 2.5 V, defined in EIA/JESD8-9B 2002 used in DDR among other things.
- SSTL_18, 1.8 V, defined in EIA/JESD8-15A, used in DDR2 among other things.
- SSTL_15, 1.5 V, used in DDR3 among other things.
SSTL_3 uses a reference of 0.45 * VDDQ (1.5 V). SSTL_2 and SSTL_18 reference a voltage that is exactly VDDQ / 2 (1.25 V and 0.9 V respectively).
SSTL_3 and SSTL_2 support two termination classes (50 ohm or 25 ohm load). SSTL_18 only supports one (25 ohm load).
See also
- High-Speed Transceiver Logic - HSTL
References
- Jaci Chang Design Considerations for the DDR3 Memory Sub-system. Jedex, 2004, p. 4. http://www.jedex.org/images/pdf/samsung%20-%20jaci_chang.pdf
- Tom Granberg Handbook of Digital Techniques for High-Speed Digital Design. Pearson Education, 2004, p. 160-161.
External links
JEDEC homepage links; require (free) login:
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