Unicore - Misplaced Pages

(Redirected from Unicore32) For the grid computing technology, see UNICORE.

Unicore
Registers
Designer	Microprocessor Research and Development Center
Bits	32-bit
Introduced	1999
Design	RISC
Encoding	Fixed
Branching	Condition code
Endianness	Little
Page size	4 KiB
General-purpose	31
Floating point	32

Unicore is a computer instruction set architecture designed by the Microprocessor Research and Development Center (MPRC) of Peking University in the PRC. The computer built on this architecture is called the Unity-863. The CPU is integrated into a fully functional SoC to make a PC-like system.

The processor is very similar to the ARM architecture, but uses a different instruction set.

It is supported by the Linux kernel as of version 2.6.39. Support will be removed in Linux kernel version 5.9 as nobody seems to maintain it and the code is falling behind the rest of the kernel code and compiler requirements.

Instruction set

The instructions are almost identical to the standard ARM formats, except that conditional execution has been removed, and the bits reassigned to expand all the register specifiers to 5 bits. Likewise, the immediate format is 9 bits rotated by a 5-bit amount (rather than 8 bit rotated by 4), the load/store offset sizes are 14 bits for byte/word and 10 bits for signed byte or half-word. Conditional moves are provided by encoding the condition in the (unused by ARM) second source register field Rn for MOV and MVN instructions.

Unicore32 instruction set overview
31	30	29	28	27	26	25	24	23	18	13	8	7	6	5	4	Description
0	0	0	opcode				S	Rn	Rd	shift	0	Sh		0	Rm	ALU operation, Rd = Rn op Rm shift #shift
0	0	0	opcode				S	Rn	Rd	Rs	0	Sh		1	Rm	ALU operation, Rd = Rn op Rm shift Rs
0	0	1	opcode				S	Rn	Rd	shift	imm9					ALU operation, Rd = Rn op #imm9 ROTL #shift
0	1	0	P	U	B	W	L	Rn	Rd	shift	0	Sh		0	Rm	Load/store Rd to address Rn ± Rm shift #shift
0	1	1	P	U	B	W	L	Rn	Rd	offset14						Load/store Rd to address Rn ± offset14
1	0	0	P	U	S	W	L	Rn	Bitmap high		0	0	H	Bitmap low		Load/store multiple registers
1	0	1	cond				L	offset24								Branch (and link) if condition true
1	1	0														Coprocessor (FPU) instructions
1	1	1	1	1	1	1	1	Trap number								Software interrupt

0	0	0	0	0	0	A	S	Rn	Rd	Rs	1	0	0	1	Rm	Multiply, Rd = Rm * Rs (+ Rn)
0	0	0	1	0	0	0	L	11111	11111	00000	1	0	0	1	Rm	Branch and exchange (BX, BLX)
0	1	0	P	U	0	W	L	Rn	Rd	00000	1	S	H	1	Rm	Load/store Rd to address Rn ± Rm (16-bit)
0	1	0	P	U	1	W	L	Rn	Rd	imm_hi	1	S	H	1	imm_lo	Load/store Rd to address Rn ± #imm10 (16-bit)

The meaning of various flag bits (such as S=1 enables setting the condition codes) is identical to the ARM instruction set. The load/store multiple instruction can only access half of the register set, depending on the H bit. If H=0, the 16 bits indicate R0–R15; if H=1, R16–R31.

References

"Introduction to MPRC". Microprocessor Research and Develop Center, Peking University.
Xu Cheng; Xiaoyin Wang; Junlin Lu; Jiangfang Yi; Dong Tong; Xuetao Guan; Feng Liu; Xianhua Liu; Chun Yang; Yi Feng (March 2010), "Research Progress of UniCore CPUs and PKUnity SoCs" (PDF), Journal of Computer Science and Technology (JCST), 25 (2): 200–213, doi:10.1007/s11390-010-9317-1, S2CID 7083916, retrieved 2012-07-11
Bergmann, Arnd (2012-07-09). "Re: [PATCH 00/36] AArch64 Linux kernel port". linux-kernel (Mailing list). Retrieved 2012-07-11. Another interesting example is unicore32, which actually shares more code with arch/arm than the proposed arch/aarch64 does. I think the unicore32 code base would benefit from being merged back into arch/arm as a third instruction set, but the additional maintenance cost for everyone working on ARM makes that unrealistic.
"Merge window closed - 2.6.39-rc1 out". Linus Torvalds.
"remove unicore32 support". Mike Rapoport.
Hsu-Hung Chiang; Huang-Jia Cheng; Yuan-Shin Hwan (2012-02-25), "Doubling the Number of Registers on ARM Processors" (PDF), 16th Workshop on Interaction between Compilers and Computer Architectures (INTERACT), pp. 1–8, doi:10.1109/INTERACT.2012.6339620, ISBN 978-1-4673-2613-1, S2CID 6832041
Unicore processor simulator source code. Instruction formats are in decode.c, disassembly in interpret.c, and emulation in instEx.c.
QEMU Unicore32 emulator source code

v t e Reduced instruction set computer (RISC) architectures
Origins	IBM 801 Berkeley RISC Stanford MIPS
In active development	Analog Devices Blackfin ARC ARM AVR eSi-RISC LatticeMico8, LatticeMico32 MIPS OpenRISC Power ISA Renesas M32R, SuperH, V850 RISC-V SPARC Sunway Unicore Xilinx MicroBlaze, PicoBlaze
Development discontinued	Alpha AMD Am29000 Apollo PRISM Atmel AVR32 Clipper CR16 CRISP DEC PRISM Intel i860, i960 META MIPS-X Motorola 88000, M·CORE PA-RISC POWER, PowerPC (active use in space exploration as RAD750), ROMP

Processor technologies

Models

Architecture

Instruction set
architectures

Types	Orthogonal instruction set CISC RISC Application-specific EDGE TRIPS VLIW EPIC MISC OISC NISC ZISC VISC architecture Quantum computing Comparison Addressing modes
Instruction sets	Motorola 68000 series VAX PDP-11 x86 ARM Stanford MIPS MIPS MIPS-X Power POWER PowerPC Power ISA Clipper architecture SPARC SuperH DEC Alpha ETRAX CRIS M32R Unicore Itanium OpenRISC RISC-V MicroBlaze LMC System/3x0 S/360 S/370 S/390 z/Architecture Tilera ISA VISC architecture Epiphany architecture Others

Execution

Instruction pipelining	Pipeline stall Operand forwarding Classic RISC pipeline
Hazards	Data dependency Structural Control False sharing
Out-of-order	Scoreboarding Tomasulo's algorithm Reservation station Re-order buffer Register renaming Wide-issue
Speculative	Branch prediction Memory dependence prediction

Parallelism

Level	Bit Bit-serial Word Instruction Pipelining Scalar Superscalar Task Thread Process Data Vector Memory Distributed
Multithreading	Temporal Simultaneous Hyperthreading Simultaneous and heterogenous Speculative Preemptive Cooperative
Flynn's taxonomy	SISD SIMD Array processing (SIMT) Pipelined processing Associative processing SWAR MISD MIMD SPMD

Processor
performance

Transistor count
Instructions per cycle (IPC)
- Cycles per instruction (CPI)
Instructions per second (IPS)
Floating-point operations per second (FLOPS)
Transactions per second (TPS)
Synaptic updates per second (SUPS)
Performance per watt (PPW)
Cache performance metrics
Computer performance by orders of magnitude

Types

By application	Embedded system Microprocessor Microcontroller Mobile Ultra-low-voltage ASIP Soft microprocessor
Systems on chip	System on a chip (SoC) Multiprocessor (MPSoC) Cypress PSoC Network on a chip (NoC)
Hardware accelerators	Coprocessor AI accelerator Graphics processing unit (GPU) Image processor Vision processing unit (VPU) Physics processing unit (PPU) Digital signal processor (DSP) Tensor Processing Unit (TPU) Secure cryptoprocessor Network processor Baseband processor

Word size

Core count

Components

Functional units	Arithmetic logic unit (ALU) Address generation unit (AGU) Floating-point unit (FPU) Memory management unit (MMU) Load–store unit Translation lookaside buffer (TLB) Branch predictor Branch target predictor Integrated memory controller (IMC) Memory management unit Instruction decoder
Logic	Combinational Sequential Glue Logic gate Quantum Array
Registers	Processor register Status register Stack register Register file Memory buffer Memory address register Program counter
Control unit	Hardwired control unit Instruction unit Data buffer Write buffer Microcode ROM Counter
Datapath	Multiplexer Demultiplexer Adder Multiplier CPU Binary decoder Address decoder Sum-addressed decoder Barrel shifter
Circuitry	Integrated circuit 3D Mixed-signal Power management Boolean Digital Analog Quantum Switch

Power
management

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