The following pages link to Instructions per cycle
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- One-instruction set computer (links | edit)
- Z3 (computer) (links | edit)
- Digital signal processor (links | edit)
- Multiple instruction, multiple data (links | edit)
- Cyrix (links | edit)
- Pentium 4 (links | edit)
- Performance Rating (links | edit)
- Memory management unit (links | edit)
- Apollo Guidance Computer (links | edit)
- Athlon 64 (links | edit)
- IAS machine (links | edit)
- Instruction pipelining (links | edit)
- Clock rate (links | edit)
- Instruction-level parallelism (links | edit)
- Power management (links | edit)
- Barrel shifter (links | edit)
- Simultaneous multithreading (links | edit)
- Speculative execution (links | edit)
- Memory-mapped I/O and port-mapped I/O (links | edit)
- Back-side bus (links | edit)
- PowerPC 970 (links | edit)
- Mobile processor (links | edit)
- Coprocessor (links | edit)
- Index register (links | edit)
- Hazard (computer architecture) (links | edit)
- Sum-addressed decoder (links | edit)
- Classic RISC pipeline (links | edit)
- Branch predictor (links | edit)
- Execution (computing) (links | edit)
- Adder (electronics) (links | edit)
- Register renaming (links | edit)
- Prefetch input queue (links | edit)
- Von Neumann architecture (links | edit)
- Processor register (links | edit)
- DEC PRISM (links | edit)
- 4-bit computing (links | edit)
- Translation lookaside buffer (links | edit)
- Instruction cycle (links | edit)
- NetBurst (links | edit)
- NX bit (links | edit)
- Explicitly parallel instruction computing (links | edit)
- Addressing mode (links | edit)
- CPU cache (links | edit)
- CORDIC (links | edit)
- Temporal multithreading (links | edit)
- 36-bit computing (links | edit)
- Multiple instruction, single data (links | edit)
- Out-of-order execution (links | edit)
- Single instruction, single data (links | edit)