Misplaced Pages

In computer architecture, a control bus is part of the system bus and is used by CPUs for communicating with other devices within the computer. While the address bus carries the information about the device with which the CPU is communicating and the data bus carries the actual data being processed, the control bus carries commands from the CPU and returns status signals from the devices. For example, if the data is being read or written to the device the appropriate line (read or write) will be active (logic one).

Lines

The number and type of lines in a control bus varies but there are basic lines common to all microprocessors, such as:

• Read (${\displaystyle {\overline {RD}}}$). A single line that when active (logic zero) indicates the device is being read by the CPU.
• Write (${\displaystyle {\overline {WR}}}$). A single line that when active (logic zero) indicates the device is being written by the CPU.
• Byte enable (${\displaystyle {\overline {E}}}$). A group of lines that indicate the size of the data (8, 16, 32, 64 bytes).

The RD and WR signals of the control bus control the reading or writing of RAM, avoiding bus contention on the data bus.

Additional lines are microprocessor-dependent, such as:

• Transfer ACK ("acknowledgement"). Delivers information that the data was acknowledged (read) by the device.
• Bus request (BR, BREQ, or BRQ). Indicates a device is requesting the use of the (data) bus.
• Bus grant (BG or BGRT). Indicates the CPU has granted access to the bus.
• Interrupt request (IRQ). A device with lower priority is requesting access to the CPU.
• Clock signals. The signal on this line is used to synchronize data between the CPU and a device.
• Reset. If this line is active, the CPU will perform a hard reboot.

Systems that have more than one bus master have additional control bus signals that control which bus master drives the address bus, avoiding bus contention on the address bus.

See also

• Address bus
• Data bus
• Bus mastering

References

1. ^ Ian Sinclair; John Dunton. "Practical Electronics Handbook". 2013. section "The control bus". p. 209-210.

External links

• Definition by Webopedia.
• Computer system organization at the University of California, Riverside.
• "Hardware and Software Architecture", a PowerPoint presentation at California State University, Los Angeles.

v t e Technical and de facto standards for wired computer buses
General	System bus Front-side bus Back-side bus Daisy chain Control bus Address bus Bus contention Bus mastering Network on a chip Plug and play List of bus bandwidths
Standards	SS-50 bus S-100 bus Multibus Unibus VAXBI MBus STD Bus SMBus Q-Bus Europe Card Bus ISA STEbus Zorro II Zorro III CAMAC FASTBUS LPC HP Precision Bus EISA VME VXI VXS VPX NuBus TURBOchannel MCA SBus VLB HP GSC bus InfiniBand Ethernet UPA PCI PCI Extended (PCI-X) PXI PCI Express (PCIe) AGP Compute Express Link (CXL) Direct Media Interface (DMI) RapidIO Intel QuickPath Interconnect NVLink HyperTransport Infinity Fabric Intel Ultra Path Interconnect Coherent Accelerator Processor Interface (CAPI) SpaceWire
Storage	ST-506 ESDI IPI SMD Parallel ATA (PATA) Bus and Tag DSSI HIPPI Serial ATA (SATA) SCSI Parallel SAS ESCON Fibre Channel SSA SATAe PCI Express (via AHCI or NVMe logical device interface)
Peripheral	Apple Desktop Bus Atari SIO DCB Commodore bus HP-IL HIL MIDI RS-232 RS-422 RS-423 RS-485 Lightning DMX512-A IEEE-488 (GPIB) IEEE-1284 (parallel port) IEEE-1394 (FireWire) UNI/O 1-Wire I²C (ACCESS.bus, PMBus, SMBus) I3C SPI D²B Parallel SCSI Profibus USB Camera Link External PCIe Thunderbolt
Audio	ADAT Lightpipe AES3 Intel HD Audio I²S MADI McASP S/PDIF TOSLINK
Portable	PC Card ExpressCard
Embedded	Multidrop bus CoreConnect AMBA (AXI) Wishbone SLIMbus
Interfaces are listed by their speed in the (roughly) ascending order, so the interface at the end of each section should be the fastest. Category

This computer hardware article is a stub. You can help Misplaced Pages by expanding it.

• v
• t
• e

• Computer buses
• Computer hardware stubs