(Redirected from List of MIPS microarchitectures )
Main article: MIPS architecture processors
This is a list of processors that implement the MIPS instruction set architecture , sorted by year, process size , frequency, die area, and so on. These processors are designed by Imagination Technologies , MIPS Technologies , and others. It displays an overview of the MIPS processors with performance and functionality versus capabilities for the more recent MIPS Aptiv families.
MIPS Computer Systems/MIPS Technologies
MIPS version
Processor
Year
Process (nm)
Frequency (MHz)
Transistors (millions)
Die area (mm)
Pin count
Power (W)
Voltage (V)
D. cache (KB)
I. cache (KB)
MMU
L2 cache
L3 cache
Features
MIPS I
R2000
1985
2000
8 to 16.67
0.11
80
64 external
64 external
none
none
5 stage pipelines, FPU: 2010
R3000
1988
1200
16.67 to 40
0.11
40
145, 172
4
32-256 external
32-256 external
0-1 MB external
none
same as R2000; FPU: 3010
MIPS II
R6000
1990
60 to 66
external
external
none
none
32-bit register size, 36-bit physical address, FPU
MIPS III
R4000
1991
800
100
1.35
213
179
15
5
8
8
128 KB to 4 MB external
none
R4400
1992
600
100 to 250
2.3
186
179
15
5, 3.3
16
16
128 KB to 4 MB external
none
R4200
1993
600
80
1.3
81
179
1.8-2.0
3.3
8
16
128 KB to 4 MB external
none
scalar design with a five-stage classic RISC pipeline
R4300i
1995
350
100 / 133
45
120
2.2
3.3
none
R4600
1994
640
100 / 133
2.2
77
179
4.6
5
16
16
512 KB external
none
R4650
1994
640
133 / 180
2.2
77
179
4.6
5
16
16
512 KB external
none
R4640
1995
640
179
none
R4700
1996
500
100 to 200
2.2
179
16
16
External
none
MIPS IV
R5000
1996
350
150 to 200
3.7
84
223
10
3.3
32
32
1 MB external
none
RM7000
1998
250, 180, 130
250 to 600
18
91
304
10, 6, 3
3.3, 2.5, 1.5
16
16
256 KB internal
1 MB external
R8000
1994
700
75 to 90
2.6
299
591
30
3.3
16
16
4 MB external
none
superscalar , up to 4 instructions per cycle
R10000
1996
350, 250
150 to 250
6.7
350
599
30
3.3
32
32
512 KB – 16 MB external
none
R12000
1998
350, 250
270 to 360
7.15
229
600
20
4
32
32
512 KB – 16 MB external
none
single-chip 4-issue superscalar
R12000A
2000
180
400
none
R14000
2001
130
500
7.2
204
527
17
32
32
512 KB – 16 MB external
none
R14000A
2002
130
600
17
32
32
none
R16000
2003
110
700 to 1000
20
64
64
512 KB – 16 MB external
none
R16000A
2004
110
800 to 1000
64
64
none
R18000
2001
130
1.2
1 MB
none
was planned, but not manufactured
MIPS V
H1 "Beast"
none
was planned, but not manufactured
H2 "Captain"
none
was planned, but not manufactured
MIPS32
4K
1999
180
167
2.5
none
4KE
90
420
1.2
none
24K
2003
130, 65, 40
400 (130 nm) 750 (65 nm) 1468 (40 nm)
0.83
0 to 64
0 to 64
4–16 MB external
none
24KE
2003
130, 65, 40
none
34K
2006
90, 65, 40
500 (90 nm) 1454 (40 nm)
none
74K
2007
65
1110
2.5
0 to 64
0 to 64
none
1004K
2008
65
1100
4.7
8 to 64
8 to 64
none
M14K
2009
130
200
none
MicroMIPS
1074K
2010
40
1500
none
1074Kf
2010
40
none
Floating point
microAptiv
2012
90, 65
8 to 64
8 to 64
none
interAptiv
2012
4 to 64
4 to 64
up to 8 MB internal
none
proAptiv
2012
32 or 64
32 or 64
up to 8 MB internal
none
MIPS64
5K
1999
20K
2000
MIPS version
Processor
Year
Process (nm)
Frequency (MHz)
Transistors (millions)
Die area (mm)
Pin count
Power (W)
Voltage (V)
D. cache (KB)
I. cache (KB)
MMU
L2 cache
L3 cache
Features
Imagination Technologies
MIPS Technologies was acquired 17 December 2012, by Imagination Technologies . Since then, the following processors have been introduced by Imagination Technologies.
Imagination Technologies sold MIPS processor rights to Tallwood MIPS Inc in 2017. MIPS Technologies was acquired by Wave Computing in 2018, where "MIPS operates as an IP licensing business unit".
The Warrior P-Class CPU was announced on 14 October 2013.
The CPU IP cores comprising the MIPS Series5 ‘Warrior’ family are based on MIPS32 release 5 and MIPS64 release 6 , and will come in three classes of performance and features:
'Warrior M-class': entry-level MIPS cores for embedded and microcontroller applications, a progression from the popular microAptiv family
'Warrior I-class': mid-range, feature-rich MIPS CPUs following on from the highly efficient interAptiv family. The I6400, with its 64-bit core, was launched September 2014.
'Warrior P-class': high-performance MIPS processors building on the proAptiv family
MIPS version
level
Processor
Year
Process (nm)
Frequency (GHz)
Transistors (billions)
Die area (mm)
Pin count
Power (W)
Voltage (V)
D. cache (KB)
I. cache (KB)
MMU
L2 cache
L3 cache
Features
MIPS32 Release 5
Warrior-P
P5600
2013
?
1.0 to 2.0
?
?
?
?
?
32/64
32/64
TLb
Up to 8 MB external
none
VZ, MSA
Warrior-M
M5100
2014
65/28
0.1 to 0.497
?
0.04 to 0.77
?
none
none
FMT
none
none
VZ
Warrior-M
M5150
2014
65/28
0.372/0.576
?
0.89/0.26
?
up to 64
up to 64
TLB
none
none
VZ
MIPS64 Release 6
Warrior-P
P6600
2015
28
Up to 2.0
?
?
?
?
?
32/64
32/64
TLB
0.5 - 8 MB external
none
SMT, VZ
Warrior-I
I6400
2014
28
1.0
?
1/core
?
?
?
32/64
32/64
TLB
0.5 - 8 MB external
none
SMT, VZ
Warrior-M
M6200
2015
65/40/28
up to 0.750
?
0.19
?
none
none
FMT
none
none
Warrior-M
M6250
2015
65/40/28
up to 0.750
?
0.23
?
up to 64
up to 64
TLB
none
none
XPA
MIPS version
level
Processor
Year
Process (nm)
Frequency (GHz)
Transistors (billions)
Die area (mm)
Pin count
Power (W)
Voltage (V)
D. cache (KB)
I. cache (KB)
MMU
L2 cache
L3 cache
Features
Other designers
A number of companies licensed the MIPS architecture and developed their own processors.
MIPS version
Licensee
Processor
Features
Year
Process (nm)
Frequency (MHz)
Transistors (millions)
Die size (mm)
Pin count
Power (W)
Voltage (V)
D. cache (KB)
I. cache (KB)
MMU
L2 cache
L3 cache
MIPS I
Lexra
LX4080, LX4180, LX4280, LX5280, LX8000
MIPS II
НИИСИ РАН
KOMDIV-32
MIPS III
Sony Computer Entertainment + Toshiba
Emotion Engine
НИИСИ РАН
KOMDIV-64
MIPS32
Alchemy Semiconductor
Au1
Broadcom
BMIPS3000
BMIPS4000
BMIPS5000
1300
BCM53001
65
400
32
32
BCM1255
Ingenic Semiconductor
XBurst 1
single issue, 8-stage pipeline
2005
180, 130, 64, 40
240
0.15
1.8
16
16
yes
none
none
XBurst 2
dual-issue/dual-threaded
2013
40
1200
0.15
1.8
32
32
yes
512
none
MIPS64
SiByte
SB1
Broadcom
BCM1125H
400-800
4w @ 400 MHz
32
32
yes
256 KB
BCM1255
Dual-core, DDR2, 4× Gigabit LAN
800-1200
13 W @ 1 GHz
32
32
yes
512 KB
Cavium
Octeon: CN30xx, CN31xx, CN36xx, CN38xx
2006
Octeon Plus: CN5xxx
2007
Octeon II: CN6xxx
2009
Octeon III: CN7xxx
2012
NEC
VR4305
VR4310
NXP Semiconductors
??
??
CAS: ICT
none yet
??
MIPS version
Licensee
Processor
Features
Year
Process (nm)
Frequency (MHz)
Transistors (millions)
Die size (mm)
Pin count
Power (W)
Voltage (V)
D. cache (KB)
I. cache (KB)
MMU
L2 cache
L3 cache
Other
References
"Completion of sale of MIPS - Imagination" . 25 October 2017.
"Wave Computing and MIPS Technologies Reach Agreement to Exit Bankruptcy" .
"About – MIPS" . Retrieved 2019-11-06.
"Imagination reveals first MIPS 'Warrior P-class' CPU core" . 2013-10-14. Retrieved 2013-10-28.
"MIPS reborn with 64-bit core launch" .
MIPS microprocessors
General processors MIPS64 compatible
Loongson 3 Series
LS3A1000/LS3A1000-I(LS3A1000-i)
LS3A2000/LS3A1500-I
LS3A3000/LS3A3000-I(LS3A3000-i)
LS3A4000/LS3A4000-I(LS3A4000-i)
LS3B1000
LS3B1500
LS3B2000
LS3B3000
LS3B4000
Application processors MIPS32 compatible
MIPS64 compatible
Microcontrollers (embedded device)M4K
4Kc/4KEc
MIPS32 compatible
Networking 4Kc/4KEc
5Kc
24Kc/24KEc
34Kc
74Kc
1004Kc
1074Kc
MIPS32 compatible
MIPS64 compatible
Gaming Supercomputer Aerospace MIPS64 compatible
MIPS32 compatible
Classic processors
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