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(Redirected from AES-NI) Instruction set extensions accelerating AES operations

An AES (Advanced Encryption Standard) instruction set is a set of instructions that are specifically designed to perform AES encryption and decryption operations efficiently. These instructions are typically found in modern processors and can greatly accelerate AES operations compared to software implementations. An AES instruction set includes instructions for key expansion, encryption, and decryption using various key sizes (128-bit, 192-bit, and 256-bit).

The instruction set is often implemented as a set of instructions that can perform a single round of AES along with a special version for the last round which has a slightly different method.

When AES is implemented as an instruction set instead of as software, it can have improved security, as its side channel attack surface is reduced.

x86 architecture processors

AES-NI (or the Intel Advanced Encryption Standard New Instructions; AES-NI) was the first major implementation. AES-NI is an extension to the x86 instruction set architecture for microprocessors from Intel and AMD proposed by Intel in March 2008.

A wider version of AES-NI, AVX-512 Vector AES instructions (VAES), is found in AVX-512.

Instructions

Instruction Description
AESENC Perform one round of an AES encryption flow
AESENCLAST Perform the last round of an AES encryption flow
AESDEC Perform one round of an AES decryption flow
AESDECLAST Perform the last round of an AES decryption flow
AESKEYGENASSIST Assist in AES round key generation
AESIMC Assist in AES decryption round key generation. Applies Inverse Mix Columns to round keys.

Intel

The following Intel processors support the AES-NI instruction set:

  • Westmere based processors, specifically:
    • Westmere-EP (a.k.a. Gulftown Xeon 5600-series DP server model) processors
    • Clarkdale processors (except Core i3, Pentium and Celeron)
    • Arrandale processors (except Celeron, Pentium, Core i3, Core i5-4XXM)
  • Sandy Bridge processors:
    • Desktop: all except Pentium, Celeron, Core i3
    • Mobile: all Core i7 and Core i5. Several vendors have shipped BIOS configurations with the extension disabled; a BIOS update is required to enable them.
  • Ivy Bridge processors
    • All i5, i7, Xeon and i3-2115C only
  • Haswell processors (all except i3-4000m, Pentium and Celeron)
  • Broadwell processors (all except Pentium and Celeron)
  • Silvermont/Airmont processors (all except Bay Trail-D and Bay Trail-M)
  • Goldmont (and later) processors
  • Skylake (and later) processors

AMD

Several AMD processors support AES instructions:

Hardware acceleration in other architectures

AES support with unprivileged processor instructions is also available in the latest SPARC processors (T3, T4, T5, M5, and forward) and in latest ARM processors. The SPARC T4 processor, introduced in 2011, has user-level instructions implementing AES rounds. These instructions are in addition to higher level encryption commands. The ARMv8-A processor architecture, announced in 2011, including the ARM Cortex-A53 and A57 (but not previous v7 processors like the Cortex A5, 7, 8, 9, 11, 15 ) also have user-level instructions which implement AES rounds.

x86 CPUs offering non-AES-NI acceleration interfaces

VIA x86 CPUs and AMD Geode use driver-based accelerated AES handling instead. (See Crypto API (Linux).)

The following chips, while supporting AES hardware acceleration, do not support AES-NI:

ARM architecture

Programming information is available in ARM Architecture Reference Manual ARMv8, for ARMv8-A architecture profile (Section A2.3 "The Armv8 Cryptographic Extension").

The Marvell Kirkwood was the embedded core of a range of SoC from Marvell Technology, these SoC CPUs (ARM, mv_cesa in Linux) use driver-based accelerated AES handling. (See Crypto API (Linux).)

  • ARMv8-A architecture
    • ARM cryptographic extensions are optionally supported on ARM Cortex-A30/50/70 cores
  • Cryptographic hardware accelerators/engines

RISC-V architecture

The scalar and vector cryptographic instruction set extensions for the RISC-V architecture were ratified respectively on 2022 and 2023, which allowed RISC-V processors to implement hardware acceleration for AES, GHASH, SHA-256, SHA-512, SM3, and SM4.

Before the AES-specific instructions were available on RISC-V, a number of RISC-V chips included integrated AES co-processors. Examples include:

  • Dual-core RISC-V 64 bits Sipeed-M1 support AES and SHA256.
  • RISC-V architecture based ESP32-C (as well as Xtensa-based ESP32), support AES, SHA, RSA, RNG, HMAC, digital signature and XTS 128 for flash.
  • Bouffalo Labs BL602/604 32-bit RISC-V supports various AES and SHA variants.

POWER architecture

Since the Power ISA v.2.07, the instructions vcipher and vcipherlast implement one round of AES directly.

IBM z/Architecture

IBM z9 or later mainframe processors support AES as single-opcode (KM, KMC) AES ECB/CBC instructions via IBM's CryptoExpress hardware. These single-instruction AES versions are therefore easier to use than Intel NI ones, but may not be extended to implement other algorithms based on AES round functions (such as the Whirlpool and Grøstl hash functions).

Other architectures

  • Atmel XMEGA (on-chip accelerator with parallel execution, not an instruction)
  • SPARC T3 and later processors have hardware support for several cryptographic algorithms, including AES.
  • Cavium Octeon MIPS All Cavium Octeon MIPS-based processors have hardware support for several cryptographic algorithms, including AES using special coprocessor 3 instructions.

Performance

In AES-NI Performance Analyzed, Patrick Schmid and Achim Roos found "impressive results from a handful of applications already optimized to take advantage of Intel's AES-NI capability". A performance analysis using the Crypto++ security library showed an increase in throughput from approximately 28.0 cycles per byte to 3.5 cycles per byte with AES/GCM versus a Pentium 4 with no acceleration.

Supporting software

Most modern compilers can emit AES instructions.

A lot of security and cryptography software supports the AES instruction set, including the following notable core infrastructure:

Application beyond AES

A fringe use of the AES instruction set involves using it on block ciphers with a similarly-structured S-box, using affine transform to convert between the two. SM4, Camellia and ARIA have been accelerated using AES-NI. The AVX-512 Galois Field New Instructions (GFNI) allows implementing these S-boxes in a more direct way.

New cryptographic algorithms have been constructed to specifically use parts of the AES algorithm, so that the AES instruction set can be used for speedups. The AEGIS family, which offers authenticated encryption, runs with at least twice the speed of AES. AEGIS is an "additional finalist for high-performance applications" in the CAESAR Competition.

See also

Notes

  1. The instruction computes 4 parallel subexpressions of AES key expansion on 4 32-bit words in a double quadword (aka SSE register) on bits X for i = 3 {\displaystyle i=3} and X for i = 1 {\displaystyle i=1} only. Two parallel AES S-box substitutions Y 0 = S u b W o r d ( X 1 ) {\displaystyle Y_{0}=SubWord(X_{1})} and Y 2 = S u b W o r d ( X 3 ) {\displaystyle Y_{2}=SubWord(X_{3})} are used in AES-256 and 2 subexpressions Y 1 = R o t W o r d ( S u b W o r d ( X 1 ) ) ⊕ r c o n {\displaystyle Y_{1}=RotWord(SubWord(X_{1}))\oplus rcon} and Y 3 = R o t W o r d ( S u b W o r d ( X 3 ) ) ⊕ r c o n {\displaystyle Y_{3}=RotWord(SubWord(X_{3}))\oplus rcon} are used in AES-128, AES-192, AES-256.

References

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